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Computer Organization and Architecture
120 questions from GATE CS 2011 to 2026, newest first.
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All Computer Organization and Architecture questions
GATE CS 2026 Set 1, Q.14
Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II: List I List II P. Immediate 1. Element of an ar...
Machine Instructions and Addressing Modes
GATE CS 2026 Set 1, Q.15
Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destina...
Machine Instructions and Addressing Modes
GATE CS 2026 Set 1, Q.16
Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?
Instruction Pipelining and Hazards
GATE CS 2026 Set 1, Q.36
Consider the real valued variables , and represented using the IEEE 754 single-precision floating-point format. The binary representations of and in hexadecim...
ALU, Datapath and Control Unit
GATE CS 2026 Set 1, Q.38
The size of the physical address space of a processor is bytes. The capacity of a cache memory unit is bytes. The cache block size is bytes. The cache me...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2026 Set 1, Q.60
The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let denot...
Instruction Pipelining and Hazards
GATE CS 2026 Set 2, Q.18
Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Se...
I/O Interface, Interrupts and DMA
GATE CS 2026 Set 2, Q.44
Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three...
Machine Instructions and Addressing Modes
GATE CS 2026 Set 2, Q.52
Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2026 Set 2, Q.56
Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical addres...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2026 Set 2, Q.57
A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performa...
Instruction Pipelining and Hazards
GATE CS 2025 Set 1, Q.11
Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously...
I/O Interface, Interrupts and DMA
GATE CS 2025 Set 1, Q.27
A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the d...
ALU, Datapath and Control Unit
GATE CS 2025 Set 1, Q.36
Consider a memory system with 1M bytes of main memory and 16K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 by...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2025 Set 1, Q.37
A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to stor...
Machine Instructions and Addressing Modes
GATE CS 2025 Set 1, Q.53
A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. I...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2025 Set 2, Q.28
Which of the following is/are part of an Instruction Set Architecture of a processor?
Machine Instructions and Addressing Modes
GATE CS 2025 Set 2, Q.32
The following two signed 2's complement numbers (multiplicand M and multiplier Q) are being multiplied using Booth's algorithm: M:
1100 1101 1110 1101and Q…ALU, Datapath and Control Unit · Number Representations and Computer Arithmetic
GATE CS 2025 Set 2, Q.39
For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2025 Set 2, Q.49
Three floating point numbers and are stored in three registers and , respectively in IEEE 754 single precision format as given below in hexadecimal:...
ALU, Datapath and Control Unit · Number Representations and Computer Arithmetic
GATE CS 2025 Set 2, Q.55
Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the "hit rate" for L1 cache is 9...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2025 Set 2, Q.56
A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that th...
Instruction Pipelining and Hazards
GATE CS 2025 Set 2, Q.61
An application executes number of instructions in 6.3 seconds. There are four types of instructions, the details of which are given in the table. The duration...
ALU, Datapath and Control Unit · Instruction Pipelining and Hazards
GATE CS 2024 Set 1, Q.15
Which one of the following statements is FALSE?
I/O Interface, Interrupts and DMA
GATE CS 2024 Set 1, Q.30
Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the...
Instruction Pipelining and Hazards
GATE CS 2024 Set 1, Q.53
Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of them use the LRU (Least Rec...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2024 Set 1, Q.54
Consider a 512 GB hard disk with 32 storage surfaces. There are 4096 sectors per track and each sector holds 1024 bytes of data. The number of cylinders in the hard disk is ____...
Memory Hierarchy: Cache, Main Memory and Secondary Storage · File Systems, I/O and Disk Scheduling
GATE CS 2024 Set 1, Q.55
The baseline execution time of a program on a 2 GHz single core machine is 100 nanoseconds (ns). The code corresponding to 90% of the execution time can be fully parallelized. T...
Instruction Pipelining and Hazards · Calculus
GATE CS 2024 Set 1, Q.56
A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss rate on instruction...
Memory Hierarchy: Cache, Main Memory and Secondary Storage · Instruction Pipelining and Hazards
GATE CS 2024 Set 2, Q.11
Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which on...
I/O Interface, Interrupts and DMA
GATE CS 2024 Set 2, Q.14
The format of a single-precision floating-point number as per the IEEE 754 standard is: Sign Exponent Mantissa (1 bit) (8 bits) (23 bits) Choose the largest floating-point numbe...
ALU, Datapath and Control Unit · Number Representations and Computer Arithmetic
GATE CS 2024 Set 2, Q.31
An instruction format has the following structure:
Instruction Number: Opcode destination reg, source reg-1, source reg-2Consider the following sequence of instructions to be...Instruction Pipelining and Hazards
GATE CS 2024 Set 2, Q.57
A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operan...
Machine Instructions and Addressing Modes
GATE CS 2024 Set 2, Q.58
A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a...
Instruction Pipelining and Hazards
GATE CS 2024 Set 2, Q.61
A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally di...
Machine Instructions and Addressing Modes
GATE CS 2023, Q.33
Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is n...
Instruction Pipelining and Hazards
GATE CS 2023, Q.34
A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and c...
I/O Interface, Interrupts and DMA
GATE CS 2023, Q.41
Consider the given C-code and its corresponding assembly code, with a few operands U1–U4 being unknown. Some useful information as well as the semantics of each unique assembly...
Machine Instructions and Addressing Modes
GATE CS 2023, Q.42
A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these me...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2023, Q.45
Consider the IEEE-754 single precision floating point numbers Which one of the following corresponds to t...
ALU, Datapath and Control Unit
GATE CS 2023, Q.64
An 8-way set associative cache of size 64 KB () is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK O...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2022, Q.17
Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?
I/O Interface, Interrupts and DMA
GATE CS 2022, Q.24
Let and be two set associative cache organizations that use LRU algorithm for cache block replacement. is a write back cache and is a write through cache...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2022, Q.33
A cache memory that has a hit rate of 0.8 has an access latency 10 ns and miss penalty 100 ns. An optimization is done on the cache to reduce the miss rate. However, the optimiz...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2022, Q.41
Consider three floating point numbers A, B and C stored in registers RA, RB and RC, respectively as per IEEE-754 single precision floating point format. The 32-bit content store...
ALU, Datapath and Control Unit
GATE CS 2022, Q.54
Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the exe...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2022, Q.61
A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given pr...
Instruction Pipelining and Hazards
GATE CS 2021 Set 1, Q.32 (CS Q.22)
Consider a computer system with a byte-addressable primary memory of size bytes. Assume the computer system has a direct-mapped cache of size …
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2021 Set 1, Q.63 (CS Q.53)
A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each. The...
Instruction Pipelining and Hazards
GATE CS 2021 Set 1, Q.65 (CS Q.55)
Consider the following instruction sequence where registers R1, R2 and R3 are general purpose and denotes the content at the memory location . Instruction...
Machine Instructions and Addressing Modes
GATE CS 2021 Set 2, Q.29 (CS Q.19)
Consider a set-associative cache of size 2KB () with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32-bit addr...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2021 Set 2, Q.30 (CS Q.20)
Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular interv...
I/O Interface, Interrupts and DMA
GATE CS 2021 Set 2, Q.37 (CS Q.27)
Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements: : Read misses in a write through L1 cache do...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2021 Set 2, Q.54 (CS Q.44)
If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices represent(s) the u...
Machine Instructions and Addressing Modes
GATE CS 2021 Set 2, Q.63 (CS Q.53)
Consider a pipelined processor with 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline...
Instruction Pipelining and Hazards
GATE CS 2020, Q.13 (CS Q.3)
Consider the following statements. I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored interrupt, the CPU does polling to...
I/O Interface, Interrupts and DMA
GATE CS 2020, Q.14 (CS Q.4)
Consider the following data path diagram. Single bus CPU data path architecture diagram showing MAR, MDR, IR, PC, general registers R0 through R7, temporary registers TEMP1 and...
ALU, Datapath and Control Unit
GATE CS 2020, Q.31 (CS Q.21)
A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2020, Q.40 (CS Q.30)
A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2020, Q.53 (CS Q.43)
Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Over...
Instruction Pipelining and Hazards
GATE CS 2020, Q.54 (CS Q.44)
A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name...
Instruction Pipelining and Hazards · Number Representations and Computer Arithmetic
GATE CS 2019, Q.11 (CS Q.1)
A certain processor uses a fully associative cache of size . The cache block size is . Assume that the main memory is byte addressable and uses a...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2019, Q.12 (CS Q.2)
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by to . What is...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2019, Q.55 (CS Q.45)
A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, t...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2018, Q.15 (CS Q.5)
Consider the following processor design characteristics. I. Register-to-register arithmetic operations only II. Fixed-length instruction format III. Hardwired control unit Which...
Machine Instructions and Addressing Modes
GATE CS 2018, Q.33 (CS Q.23)
A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is . The time taken to...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2018, Q.44 (CS Q.34)
The size of the physical address space of a processor is bytes. The word length is bytes. The capacity of cache memory is bytes. The size of each cache block i...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2018, Q.60 (CS Q.50)
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback...
Instruction Pipelining and Hazards
GATE CS 2018, Q.61 (CS Q.51)
A processor has 16 integer registers (R0, R1, .. , R15) and 64 floating point registers (F0, F1,… , F63). It uses a 2-byte instruction format. There are four categories of instr...
Machine Instructions and Addressing Modes
GATE CS 2017 Set 1, Q.9 (CS Q.9)
When two 8-bit numbers and in 2's complement representation (with and as the least significant bits) are added using a ripple-carry a...
ALU, Datapath and Control Unit · Number Representations and Computer Arithmetic
GATE CS 2017 Set 1, Q.11 (CS Q.11)
Consider the C struct defined below: struct data { int marks[100]; char grade; int cnumber; }; struct data student; The base address of
studentis available in register R1. Th...Machine Instructions and Addressing Modes
GATE CS 2017 Set 1, Q.25 (CS Q.25)
Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 1, Q.49 (CS Q.49)
Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified i...
Machine Instructions and Addressing Modes
GATE CS 2017 Set 1, Q.50 (CS Q.50)
Instruction execution in a processor is divided into 5 stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stag...
Instruction Pipelining and Hazards
GATE CS 2017 Set 1, Q.51 (CS Q.51)
Consider a 2-way set associative cache with 256 blocks and uses LRU replacement. Initially the cache is empty. Conflict misses are those misses which occur due to contention of...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 1, Q.54 (CS Q.54)
A cache memory unit with capacity of words and block size of words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits....
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 2, Q.29 (CS Q.29)
In a two-level cache system, the access times of and caches are 1 and 8 clock cycles, respectively. The miss penalty from the cache to main memory is 18 clock...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 2, Q.45 (CS Q.45)
The read access times and the hit ratios for different caches in a memory hierarchy are as given below. | Cache | Read access time (in nanoseconds) | Hit ratio | | :--- | :---:...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 2, Q.53 (CS Q.53)
Consider a machine with a byte addressable main memory of bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used w...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2016 Set 1, Q.19 (CS Q.9)
A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least _...
Machine Instructions and Addressing Modes
GATE CS 2016 Set 1, Q.41 (CS Q.31)
The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addre...
I/O Interface, Interrupts and DMA
GATE CS 2016 Set 1, Q.42 (CS Q.32)
The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design invo...
Instruction Pipelining and Hazards
GATE CS 2016 Set 2, Q.20 (CS Q.10)
A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of...
Machine Instructions and Addressing Modes
GATE CS 2016 Set 2, Q.40 (CS Q.30)
Suppose the functions and can be computed in 5 and 3 nanoseconds by functional units and , respectively. Given two instances of and two instances of…
ALU, Datapath and Control Unit
GATE CS 2016 Set 2, Q.41 (CS Q.31)
Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one des...
Machine Instructions and Addressing Modes
GATE CS 2016 Set 2, Q.42 (CS Q.32)
The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is ________ bits.
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2016 Set 2, Q.43 (CS Q.33)
Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies and such that . If the longest...
Instruction Pipelining and Hazards
GATE CS 2015 Set 1, Q.18 (CS Q.8)
For computers based on three-address instruction formats, each address field can be used to specify which of the following: (S1) A memory operand (S2) A processor register (S3)...
Machine Instructions and Addressing Modes
GATE CS 2015 Set 1, Q.48 (CS Q.38)
Consider a non-pipelined processor with a clock rate of and average cycles per instruction of four. The same processor is upgraded to a pipelined processo...
Instruction Pipelining and Hazards
GATE CS 2015 Set 1, Q.58 (CS Q.48)
Consider a disk pack with a seek time of milliseconds and rotational speed of rotations per minute (RPM). It has sectors per track and each sector can store…
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2015 Set 2, Q.34 (CS Q.24)
Assume that for a certain processor, a read request takes 50 nanoseconds on a cache miss and 5 nanoseconds on a cache hit. Suppose while running a program, it was observed that...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2015 Set 2, Q.52 (CS Q.42)
Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the m...
Machine Instructions and Addressing Modes
GATE CS 2015 Set 2, Q.54 (CS Q.44)
Consider the sequence of machine instructions given below: MUL R5, R0, R1 DIV R6, R2, R3 ADD R7, R5, R6 SUB R8, R7, R4 In the above sequence, R0 to R8 are general purpose regist...
Instruction Pipelining and Hazards
GATE CS 2015 Set 3, Q.24 (CS Q.14)
Consider a machine with a byte addressable main memory of bytes, block size of 16 bytes and a direct mapped cache having cache lines. Let the addresses of two...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2015 Set 3, Q.57 (CS Q.47)
Consider the following code sequence having five instructions to . Each of these instructions has the following format.
OP Ri, Rj, Rkwhere operationOPis perfor...Instruction Pipelining and Hazards
GATE CS 2015 Set 3, Q.61 (CS Q.51)
Consider the following reservation table for a pipeline having three stages and : Stage \ Time 1 2 3 4 5 S1 X X S2 X X S3 X The minimum average latency (MAL) is...
Instruction Pipelining and Hazards
GATE CS 2014 Set 1, Q.19 (CS Q.9)
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immedi...
Machine Instructions and Addressing Modes
GATE CS 2014 Set 1, Q.53 (CS Q.43)
Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on...
Instruction Pipelining and Hazards
GATE CS 2014 Set 1, Q.54 (CS Q.44)
An access sequence of cache block addresses is of length and contains unique block addresses. The number of unique block addresses between two consecutive accesses to th...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2014 Set 1, Q.65 (CS Q.55)
Consider two processors and executing the same instruction set. Assume that under identical conditions, for the same input, a program running on takes 25% less...
ALU, Datapath and Control Unit
GATE CS 2014 Set 2, Q.19 (CS Q.9)
A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2014 Set 2, Q.53 (CS Q.43)
In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2014 Set 2, Q.54 (CS Q.44)
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2014 Set 2, Q.65 (CS Q.55)
Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nan...
I/O Interface, Interrupts and DMA
GATE CS 2014 Set 3, Q.19 (CS Q.9)
Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 n...
Instruction Pipelining and Hazards
GATE CS 2014 Set 3, Q.53 (CS Q.43)
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and regi...
Instruction Pipelining and Hazards
GATE CS 2014 Set 3, Q.54 (CS Q.44)
The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation wit...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2013, Q.20 (CS Q.20)
In a -way set associative cache, the cache is divided into sets, each of which consists of lines. The lines of a set are placed in sequence one after another. The lin...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2013, Q.28 (CS Q.28)
Consider the following sequence of micro-operations. …
I/O Interface, Interrupts and DMA
GATE CS 2013, Q.45 (CS Q.45)
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) an...
Instruction Pipelining and Hazards
GATE CS 2013, Q.46 (CS Q.46)
A RAM chip has a capacity of 1024 words of 8 bits each (). The number of decoders with enable line needed to construct a ...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2013, Q.53 (CS Q.53)
What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer?
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2012, Q.20 (CS Q.20)
Register renaming is done in pipelined processors
Instruction Pipelining and Hazards · Instruction Pipelining and Hazards
GATE CS 2012, Q.54 (CS Q.54)
The number of bits in the tag field of an address is
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2012, Q.55 (CS Q.55)
The size of the cache tag directory is
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2011, Q.11 (CS Q.11)
A computer handles several interrupt sources of which the following are relevant for this question. - Interrupt from CPU temperature sensor (raises interrupt if CPU temperature...
I/O Interface, Interrupts and DMA
GATE CS 2011, Q.21 (CS Q.21)
Consider a hypothetical processor with an instruction of type
LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The...Machine Instructions and Addressing Modes
GATE CS 2011, Q.28 (CS Q.28)
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory. ...
I/O Interface, Interrupts and DMA
GATE CS 2011, Q.41 (CS Q.41)
Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end...
Instruction Pipelining and Hazards
GATE CS 2011, Q.43 (CS Q.43)
An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag in...
Memory Hierarchy: Cache, Main Memory and Secondary Storage