GATE CS 2024 Set 2 Q.31: Instruction Pipelining and Hazards

An instruction format has the following structure:

Instruction Number: Opcode destination reg, source reg-1, source reg-2

Consider the following sequence of instructions to be executed in a pipelined processor:

I1: DIV R3, R1, R2

I2: SUB R5, R3, R4

I3: ADD R3, R5, R6

I4: MUL R7, R3, R8

Which of the following statements is/are TRUE?

There is a RAW dependency on R3 between I1 and I2

There is a WAR dependency on R3 between I1 and I3

There is a RAW dependency on R3 between I2 and I3

There is a WAW dependency on R3 between I3 and I4

Official answer and solution

Official answer: A
From: Official GATE 2024 answer key

Solution

Identify the read and write register sets of I1..I4 and check each pair for RAW (write then read), WAR (read then write), and WAW (write then write) on R3.

Tracking accesses to register R3:

I1 writes R3
I2 reads R3
I3 writes R3
I4 reads R3

Checking each statement:

(A) is TRUE: I1 writes R3 and I2 subsequently reads R3, which is a Read-After-Write (RAW) dependency.
(B) is FALSE: Both I1 and I3 write R3, which is a WAW dependency (not WAR).
(C) is FALSE: I2 reads R3 and I3 writes R3, which is a WAR anti-dependency (not RAW).
(D) is FALSE: I3 writes R3 and I4 reads R3, which is a RAW dependency (not WAW).

Final answer

Option (A)

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2024 Computer Science and Information Technology - Set 2 (CS2)
Question: 31 of 65
Section: Computer Science and Information Technology

Report an error in this question

GATE questions are the work of the organising institutes. This site is independent and is not affiliated with them.

Question

Solution

Source