GATE CS Mastery
Cheat sheets

GATE CS 2025 Set 2 · Computer Organization and Architecture

Question 56

NAT2 marksNo negative markingEasy (estimate)

Question

A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________ . (rounded off to two decimal places)

Official answer and solution
Accepted answers
260.2 to 261.2
From
Official GATE 2025 answer key

Solution

Determine the pipeline clock period Tclk=max⁡(stage delays)+TlatchT_{\text{clk}} = \max(\text{stage delays}) + T_{\text{latch}} and multiply by (k+N−1)(k + N - 1) cycles.

  1. Pipeline clock cycle time (TclkT_{\text{clk}}):
    Tclk=max⁡(180,250,150,170,250)+10=250+10=260 nsT_{\text{clk}} = \max(180, 250, 150, 170, 250) + 10 = 250 + 10 = 260\text{ ns}
  2. Total clock cycles for N=1000N = 1000 instructions in a k=5k = 5-stage pipeline without stalls:
    Cycles=k+N−1=5+1000−1=1004 cycles\text{Cycles} = k + N - 1 = 5 + 1000 - 1 = 1004\text{ cycles}
  3. Total execution time:
    T=1004×260 ns=261,040 ns=261.04 μsT = 1004 \times 260\text{ ns} = 261,040\text{ ns} = 261.04\text{ }\mu\text{s}
Final answer

261.04

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper
GATE 2025 Computer Science and Information Technology - Session 2 (CS2)
Question
56 of 65
Section
Computer Science and Information Technology

Report an error in this question

GATE questions are the work of the organising institutes. This site is independent and is not affiliated with them.