Question 52

With a $4\text{ KB} = 2^{12}$ byte direct-mapped cache and $16 = 2^4$ byte block size:

• Block offset: lowest $4$ bits (last hex digit).
• Cache index: next $\log_2(2^{12}/2^4) = 8$ bits (the two hex digits before the last hex digit).
• Tag: upper $24 - 12 = 12$ bits (first three hex digits).

Decoding the four addresses:

• P (0x845B32): Tag $= \texttt{845}$, Index $= \texttt{B3}$, Offset $= \texttt{2}$
• Q (0x845B26): Tag $= \texttt{845}$, Index $= \texttt{B2}$, Offset $= \texttt{6}$
• R (0x845B36): Tag $= \texttt{845}$, Index $= \texttt{B3}$, Offset $= \texttt{6}$
• S (0x846B32): Tag $= \texttt{846}$, Index $= \texttt{B3}$, Offset $= \texttt{2}$

Tracing the access loop P, Q, R, S:

• P maps to Index B3 (Tag 845): on iteration 1 it is a cold miss; on iterations 2..10 it is a conflict miss because S (Index B3, Tag 846) replaced block B3 at the end of the previous iteration. Thus every access to P is a miss (A is true).
• Q maps alone to Index B2 (Tag 845): misses on iteration 1, and hits on iterations 2..10 (C is false).
• R maps to the exact same memory block as P (Tag 845, Index B3), which was just loaded by P in the same iteration. Thus every access to R is a cache hit (B is true).
• S maps to Index B3 (Tag 846), which is overwritten by P in every iteration, so every access to S is a miss (D is false).