Question
A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X1 and X2. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is____________.
Official answer and solution
- Accepted answers
- 1.42 to 1.45
- From
- Official GATE 2022 answer key
Solution
Calculate the effective CPI for processors X1 and X2 and compute their speedup ratio.
Let be the number of instructions in program P, and be the fraction of branch instructions.
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For processor X1:
- Base CPI = 1.
- Every branch incurs a penalty of 2 stall cycles.
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For processor X2:
- BPU accuracy = 80% (). Correctly predicted branches incur 0 stall cycles.
- Misprediction rate = . Mispredicted branches incur the standard 2 stall cycles.
-
Speedup of X2 over X1 at the same clock frequency:
Rounding to two decimal places gives 1.43 (official key accepts range 1.42 to 1.45).
1.43
Applying the 80% branch prediction accuracy to all instructions rather than only the 30% branch instructions.
The answer is the one in the official GATE answer key. The solution is this site's own explanation.
Source
- Paper
- GATE 2022 Computer Science and Information Technology (CS)
- Question
- 61 of 65
- Section
- Computer Science and Information Technology
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