GATE CS 2021 Set 1 Q.63 (CS Q.53): Instruction Pipelining and Hazards

A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each.

The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is _____________ nanoseconds.

Your answer

Official answer and solution

Official answer: 17160
From: Official GATE 2021 answer key

Solution

Determine the pipeline clock cycle period from the slowest stage delay plus register overhead, then apply the unpipelined stall-free throughput formula.

The pipeline has $k = 5$ stages with stage delays:

\{150\text{ ns}, 120\text{ ns}, 150\text{ ns}, 160\text{ ns}, 140\text{ ns}\}

Intermediate pipeline register delay is $r = 5\text{ ns}$ .

The clock period $T_{\text{clk}}$ of the pipeline must accommodate the slowest stage plus the register overhead:

T_{\text{clk}} = \max(150, 120, 150, 160, 140) + r = 160 + 5 = 165\text{ ns}

For $n = 100$ independent instructions executed without stalls, the total number of clock cycles required is:

\text{Total cycles} = k + (n - 1) = 5 + 99 = 104\text{ cycles}

The total execution time is:

\text{Total Time} = 104 \times 165\text{ ns} = 17160\text{ ns}

Final answer

17160

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2021 Computer Science and Information Technology (CS, Set-1)
Question: 63 of 65, printed as CS Q.53
Section: Computer Science and Information Technology

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