GATE CS 2026 Set 1 Q.60: Instruction Pipelining and Hazards

The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let $t_{EX}$ denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of $t_{EX}$ and $M$ (the number of instructions of that type in a sequence of 100 instructions for a program P), are given in the table below.

The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible.

Instruction	$t_{EX}$ in nanoseconds	$M$
LOAD	1.8	15
IMUL	1.5	10
IDIV	2.5	5
FADD	1.7	10
FSUB	1.7	5
FMUL	2.8	15
FDIV	3.2	5
All other instructions	Less than 1.0	35

When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is ______. (answer in integer)

Your answer

Official answer and solution

Official answer: 95
From: Official GATE 2026 answer key

Solution

For each instruction type, compute the number of EX clock cycles $\lceil t_{EX} / 1\text{ ns} \rceil$ and the resulting stall cycles $\lceil t_{EX} \rceil - 1$ per instruction.

Since the pipeline clock cycle is $1\text{ ns}$ , an instruction requiring $t_{EX}\text{ ns}$ in the EX stage occupies the EX stage for $\lceil t_{EX} \rceil$ clock cycles, causing $\lceil t_{EX} \rceil - 1$ structural-hazard stall cycles:

LOAD ( $t_{EX} = 1.8\text{ ns}$ ): $(\lceil 1.8 \rceil - 1) \times 15 = 1 \times 15 = 15$ stalls
IMUL ( $t_{EX} = 1.5\text{ ns}$ ): $(\lceil 1.5 \rceil - 1) \times 10 = 1 \times 10 = 10$ stalls
IDIV ( $t_{EX} = 2.5\text{ ns}$ ): $(\lceil 2.5 \rceil - 1) \times 5 = 2 \times 5 = 10$ stalls
FADD ( $t_{EX} = 1.7\text{ ns}$ ): $(\lceil 1.7 \rceil - 1) \times 10 = 1 \times 10 = 10$ stalls
FSUB ( $t_{EX} = 1.7\text{ ns}$ ): $(\lceil 1.7 \rceil - 1) \times 5 = 1 \times 5 = 5$ stalls
FMUL ( $t_{EX} = 2.8\text{ ns}$ ): $(\lceil 2.8 \rceil - 1) \times 15 = 2 \times 15 = 30$ stalls
FDIV ( $t_{EX} = 3.2\text{ ns}$ ): $(\lceil 3.2 \rceil - 1) \times 5 = 3 \times 5 = 15$ stalls
All other instructions ( $t_{EX} < 1.0\text{ ns}$ ): $(1 - 1) \times 35 = 0$ stalls

Total stall clock cycles $= 15 + 10 + 10 + 10 + 5 + 30 + 15 + 0 = 95$ .

Final answer

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2026 Computer Science and Information Technology - Session 1 (CS1)
Question: 60 of 65
Section: Computer Science and Information Technology

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