Question 46

We are given:

• Available RAM chip size: $1\text{K} \times 8$ (1024 words of 8 bits each).
• Target RAM size: $16\text{K} \times 16$ (16384 words of 16 bits each).

1. Determine total number of RAM chips:

   $$\text{Number of chips} = \dfrac{16\text{K} \times 16}{1\text{K} \times 8} = 16 \times 2 = 32\text{ chips}$$
   • Each row requires $16 / 8 = 2$ chips to provide 16-bit wide data.
   • There are $16\text{K} / 1\text{K} = 16$ such rows.

2. Design the row decoder:
   To select 1 out of the 16 rows, we need a $4 \times 16$ decoder, which requires 4 address lines.
   We must build this $4 \times 16$ decoder using $2 \times 4$ decoders equipped with an enable line:

   • Second level: To drive the 16 chip-select lines (4 lines per decoder), we need:
     $$\dfrac{16}{4} = 4\text{ decoders of size } 2 \times 4$$
   • First level: To select which of the 4 second-level decoders is active, we need a decoder to produce 4 enable signals from the remaining 2 address lines:
     $$\dfrac{4}{4} = 1\text{ decoder of size } 2 \times 4$$
   • Total decoders needed:
     $$4 + 1 = 5\text{ decoders of size } 2 \times 4$$

Therefore, 5 decoders are required, which corresponds to option (B).