Question 65

Timing Parameters:

• Bus occupancy per write request = $100$ ns.
• Module cycle time per write = $100$ ns (with bus) $+ 500$ ns (thereafter) = $600$ ns total.
• Total number of memory modules = $8$.

Bottleneck Analysis:

• During the $600$ ns that one memory module is busy completing a store, the system bus is only occupied for the first $100$ ns.
• The bus is free for the remaining $500$ ns and can initiate stores to other available memory modules.
• In $600$ ns, the bus can initiate:
  $$\frac{600 \text{ ns}}{100 \text{ ns/request}} = 6 \text{ requests}.$$
• Since there are $8$ modules available and $8 \ge 6$, the memory modules do NOT saturate or stall the bus.
• Therefore, the system bus is the sole throughput bottleneck.

Maximum Initiations in 1 ms:

• The bus can initiate a new store every $100$ ns continuously.
• Time duration = $1 \text{ ms} = 10^{-3} \text{ s} = 10^6 \text{ ns}$.
• Maximum number of stores initiated:
  $$\text{Stores} = \frac{1{,}000{,}000 \text{ ns}}{100 \text{ ns/store}} = 10{,}000.$$