GATE CS 2016 Set 1 Q.41 (CS Q.31): I/O Interface, Interrupts and DMA

The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _____.

Your answer

Official answer and solution

Official answer: 456
From: Official GATE 2016 answer key

Solution

Determine the maximum byte transfer capability of the 16-bit count register and divide total file bytes by this block limit.

The data count register of the DMA controller has 16 bits. In a byte-addressable system, the maximum count of bytes that can be transferred in a single DMA operation is:

\text{Max transfer size} = 2^{16}\text{ bytes} = 65,536\text{ bytes} = 64\text{ KB}

The total file size to be transferred is:

\text{File size} = 29,154\text{ kilobytes} = 29,154 \times 1024\text{ bytes} = 29,853,696\text{ bytes}

Each time the DMA controller takes control of the system bus from the processor, it can transfer at most $65,536$ bytes. The number of bus acquisitions required is:

\text{Number of transfers} = \left\lceil \frac{29,853,696}{65,536} \right\rceil = \left\lceil \frac{29,154}{64} \right\rceil = \lceil 455.53125 \rceil = 456

Final answer

456

Common trap

Truncating or flooring to 455, leaving the final fractional block untransferred.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2016 Computer Science and Information Technology (CS) Session 1
Question: 41 of 65, printed as CS Q.31
Section: Computer Science and Information Technology

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