Question

A cache memory unit with capacity of NN words and block size of BB words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.

Official answer and solution
Official answer
14
From
Official GATE 2017 answer key

Solution

Relate cache capacity, line size, and associativity to the field widths of physical memory addresses.

Let AA be the number of bits in the physical address.
The cache has capacity NN words and block size BB words.
The number of word-offset bits within a block is log⁡2B\log_2 B.

  1. Direct Mapped Cache:
  • The number of blocks (lines) is N/BN / B.
  • In a direct mapped cache, each line forms its own set, so the number of sets is N/BN / B.
  • The number of index bits is log⁡2(N/B)\log_2(N / B).
  • The physical address is partitioned as:
    TAG+Index+Offset=A\text{TAG} + \text{Index} + \text{Offset} = A
    TAGDM=A−log⁡2(N/B)−log⁡2B=A−log⁡2N=10 bits\text{TAG}_{\text{DM}} = A - \log_2(N / B) - \log_2 B = A - \log_2 N = 10\text{ bits}
  1. 16-way Set-Associative Cache:
  • Associativity P=16P = 16.
  • The number of sets is:
    Sets=N/B16\text{Sets} = \frac{N / B}{16}
  • The number of set-index bits is:
    IndexSA=log⁡2(N/B16)=log⁡2(N/B)−log⁡2(16)=log⁡2(N/B)−4\text{Index}_{\text{SA}} = \log_2\left(\frac{N / B}{16}\right) = \log_2(N / B) - \log_2(16) = \log_2(N / B) - 4
  • Because the physical address width AA and block size BB remain the same, decreasing the index field by 4 bits increases the TAG field by 4 bits:
    TAGSA=TAGDM+4=10+4=14 bits\text{TAG}_{\text{SA}} = \text{TAG}_{\text{DM}} + 4 = 10 + 4 = 14\text{ bits}
Final answer

14.0

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper
GATE 2017 Computer Science and Information Technology (CS) Session 1
Question
54 of 65, printed as CS Q.54
Section
Computer Science and Information Technology

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