Question
A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.
R-type Instruction Format:
| Field 1 | Field 2 | Field 3 | Field 4 | Field 5 |
|---|---|---|---|---|
| OPCODE | UNUSED | DST Register | SRC Register1 | SRC Register 2 |
I-type Instruction Format:
| Field 1 | Field 2 | Field 3 | Field 4 |
|---|---|---|---|
| OPCODE | DST Register | SRC Register | # Immediate value/address |
In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.
Let be the number of bits used to encode the UNUSED field, be the number of bits used to encode the OPCODE field, and be the number of bits used to encode the immediate value/address field. The value of is ________
Official answer and solution
- Official answer
- 34
- From
- Official GATE 2024 answer key
Solution
Compute the bit-widths of the OPCODE field (), each register field, the UNUSED field (), and the Immediate field ().
- OPCODE field size ():
- The instructions are equally divided into R-type and I-type instructions.
- Encoding operations of each type requires bits, plus bit to distinguish R-type vs. I-type:
- Register field size:
- To address architectural registers, each register field requires bits.
- UNUSED field size () in 32-bit R-type format (which has 3 register fields):
- Immediate value/address field size () in 32-bit I-type format (which has 2 register fields):
- Final value:
34
The answer is the one in the official GATE answer key. The solution is this site's own explanation.
Source
- Paper
- GATE 2024 Computer Science and Information Technology - Set 2 (CS2)
- Question
- 61 of 65
- Section
- Computer Science and Information Technology
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