Question
Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?
Official answer and solution
- Official answer
- B
- From
- Official GATE 2026 answer key
Solution
Identify the true data dependency (RAW) that causes a data hazard in an in-order instruction pipeline.
In a standard in-order pipelined processor, instructions read their source registers in an early stage (ID) and write their destination register in a late stage (WB). When a subsequent instruction needs to read a register written by a preceding instruction before that write completes, a Read-after-write (RAW) true data dependency causes a data hazard.
Option (B)
The answer is the one in the official GATE answer key. The solution is this site's own explanation.
Source
- Paper
- GATE 2026 Computer Science and Information Technology - Session 1 (CS1)
- Question
- 16 of 65
- Section
- Computer Science and Information Technology
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