Question

Consider a 2-way set associative cache with 256 blocks and uses LRU replacement. Initially the cache is empty. Conflict misses are those misses which occur due to contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks:

(0,128,256,128,0,128,256,128,1,129,257,129,1,129,257,129)(0, 128, 256, 128, 0, 128, 256, 128, 1, 129, 257, 129, 1, 129, 257, 129)

is repeated 10 times. The number of conflict misses experienced by the cache is ______.

Official answer and solution
Official answer
76
From
Official GATE 2017 answer key

Solution

Simulate LRU set-associative cache line replacements across the 10 iterations to classify compulsory versus conflict misses.

Cache configuration:

  • Total cache blocks = 256.
  • 2-way set-associative   ⟹  \implies Number of sets = 256/2=128256 / 2 = 128 sets (indexed 0 to 127).
  • Set index of block BB is B mod 128B \bmod 128.

The sequence of accesses is:

(0,128,256,128,0,128,256,128,1,129,257,129,1,129,257,129)(0, 128, 256, 128, 0, 128, 256, 128, 1, 129, 257, 129, 1, 129, 257, 129)

Notice that:

  • Blocks 0, 128, 256 all map to set 00 (0 mod 128=128 mod 128=256 mod 128=00 \bmod 128 = 128 \bmod 128 = 256 \bmod 128 = 0).
  • Blocks 1, 129, 257 all map to set 11 (1 mod 128=129 mod 128=257 mod 128=11 \bmod 128 = 129 \bmod 128 = 257 \bmod 128 = 1).
    Because sets 0 and 1 are completely independent and exhibit identical access sequences, we can trace set 0 and double the result.

Trace set 0 for the 8 accesses (0, 128, 256, 128, 0, 128, 256, 128):

  • Iteration 1:
    1. Access 0: Miss (Compulsory 1), Cache = [0]
    2. Access 128: Miss (Compulsory 2), Cache = [0, 128]
    3. Access 256: Miss (Compulsory 3), replaces 0, Cache = [128, 256]
    4. Access 128: Hit, Cache = [256, 128]
    5. Access 0: Miss (Conflict 1), replaces 256, Cache = [128, 0]
    6. Access 128: Hit, Cache = [0, 128]
    7. Access 256: Miss (Conflict 2), replaces 0, Cache = [128, 256]
    8. Access 128: Hit, Cache = [256, 128]
      Iteration 1 for Set 0 yields: 3 Compulsory misses, 2 Conflict misses, 3 Hits. Cache end state: [256, 128].
  • Iterations 2 through 10 (each iteration starts with cache = [256, 128]):
    1. Access 0: Miss (Conflict), replaces 256, Cache = [128, 0]
    2. Access 128: Hit, Cache = [0, 128]
    3. Access 256: Miss (Conflict), replaces 0, Cache = [128, 256]
    4. Access 128: Hit, Cache = [256, 128]
    5. Access 0: Miss (Conflict), replaces 256, Cache = [128, 0]
    6. Access 128: Hit, Cache = [0, 128]
    7. Access 256: Miss (Conflict), replaces 0, Cache = [128, 256]
    8. Access 128: Hit, Cache = [256, 128]
      Each subsequent iteration experiences exactly 4 Conflict misses and 4 Hits!

Total conflict misses for Set 0 over 10 iterations:

ConflictSet 0=2+(9×4)=2+36=38\text{Conflict}_{\text{Set } 0} = 2 + (9 \times 4) = 2 + 36 = 38

By symmetry, Set 1 also experiences 38 conflict misses.
Total conflict misses across the entire cache:

Total Conflict Misses=38+38=76\text{Total Conflict Misses} = 38 + 38 = 76
Final answer

76.0

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper
GATE 2017 Computer Science and Information Technology (CS) Session 1
Question
51 of 65, printed as CS Q.51
Section
Computer Science and Information Technology

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