GATE CS 2012 Q.20 (CS Q.20): Instruction Pipelining and Hazards

as an alternative to register allocation at compile time

for efficient access to function parameters and local variables

to handle certain kinds of hazards

as part of address translation

Official answer and solution

Solution

Identify the purpose and mechanism of register renaming in pipelined and superscalar processors.

In pipelined and out-of-order execution processors, instructions can suffer from three categories of data hazards:

RAW (Read-After-Write): true data dependency where an instruction consumes data produced by an earlier instruction.
WAR (Write-After-Read): anti-dependency where an instruction writes to a register before a previous instruction has finished reading its older value.
WAW (Write-After-Write): output dependency where two instructions write to the same register in different pipeline cycles.

WAR and WAW are false (or name) dependencies caused by having a finite number of architectural register names rather than an actual flow of computed values.
Register renaming solves this problem by dynamically remapping architectural registers to a larger pool of physical register locations. This eliminates false dependencies (WAR and WAW hazards) without stalling the execution pipeline.
Therefore, register renaming is done in pipelined processors to handle certain kinds of hazards.

Final answer

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