GATE CS 2026 Set 1 Q.14: Machine Instructions and Addressing Modes

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II:

List I	List II
P. Immediate	1. Element of an array
Q. Indirect	2. Pointer
R. Base with index	3. Element of a record
S. Base with offset/displacement	4. Constant

P-4, Q-3, R-1, S-2

P-4, Q-2, R-1, S-3

P-1, Q-4, R-3, S-2

P-2, Q-3, R-1, S-4

Official answer and solution

Solution

Map each hardware addressing mode to the high-level language construct it directly supports.

P. Immediate (4. Constant): The operand value is embedded directly in the instruction as a literal constant.
Q. Indirect (2. Pointer): The register or memory operand holds the effective address of the target data, implementing pointer dereferencing.
R. Base with index (1. Element of an array): Adds a base address register and an index register (Base + Index), matching array indexing A[i].
S. Base with offset/displacement (3. Element of a record): Adds a constant compile-time field offset to a base pointer (Base + Offset), matching struct/record member access rec.field.

Final answer

Option (B)

Common trap

Swapping R (Base with index) and S (Base with offset/displacement).

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Paper: GATE 2026 Computer Science and Information Technology - Session 1 (CS1)
Question: 14 of 65
Section: Computer Science and Information Technology

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