Computer Organization and Architecture · Previous year questions
Machine Instructions and Addressing Modes
21 questions from GATE CS 2011 to 2026, newest first.
Questions
GATE CS 2026 Set 1, Q.14
Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II: List I List II P. Immediate 1. Element of an ar...
Machine Instructions and Addressing Modes
GATE CS 2026 Set 1, Q.15
Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destina...
Machine Instructions and Addressing Modes
GATE CS 2026 Set 2, Q.44
Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three...
Machine Instructions and Addressing Modes
GATE CS 2025 Set 1, Q.37
A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to stor...
Machine Instructions and Addressing Modes
GATE CS 2025 Set 2, Q.28
Which of the following is/are part of an Instruction Set Architecture of a processor?
Machine Instructions and Addressing Modes
GATE CS 2024 Set 2, Q.57
A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operan...
Machine Instructions and Addressing Modes
GATE CS 2024 Set 2, Q.61
A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally di...
Machine Instructions and Addressing Modes
GATE CS 2023, Q.41
Consider the given C-code and its corresponding assembly code, with a few operands U1–U4 being unknown. Some useful information as well as the semantics of each unique assembly...
Machine Instructions and Addressing Modes
GATE CS 2021 Set 1, Q.65 (CS Q.55)
Consider the following instruction sequence where registers R1, R2 and R3 are general purpose and denotes the content at the memory location . Instruction...
Machine Instructions and Addressing Modes
GATE CS 2021 Set 2, Q.54 (CS Q.44)
If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices represent(s) the u...
Machine Instructions and Addressing Modes
GATE CS 2018, Q.15 (CS Q.5)
Consider the following processor design characteristics. I. Register-to-register arithmetic operations only II. Fixed-length instruction format III. Hardwired control unit Which...
Machine Instructions and Addressing Modes
GATE CS 2018, Q.61 (CS Q.51)
A processor has 16 integer registers (R0, R1, .. , R15) and 64 floating point registers (F0, F1,… , F63). It uses a 2-byte instruction format. There are four categories of instr...
Machine Instructions and Addressing Modes
GATE CS 2017 Set 1, Q.11 (CS Q.11)
Consider the C struct defined below: struct data { int marks[100]; char grade; int cnumber; }; struct data student; The base address of
studentis available in register R1. Th...Machine Instructions and Addressing Modes
GATE CS 2017 Set 1, Q.49 (CS Q.49)
Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified i...
Machine Instructions and Addressing Modes
GATE CS 2016 Set 1, Q.19 (CS Q.9)
A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least _...
Machine Instructions and Addressing Modes
GATE CS 2016 Set 2, Q.20 (CS Q.10)
A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of...
Machine Instructions and Addressing Modes
GATE CS 2016 Set 2, Q.41 (CS Q.31)
Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one des...
Machine Instructions and Addressing Modes
GATE CS 2015 Set 1, Q.18 (CS Q.8)
For computers based on three-address instruction formats, each address field can be used to specify which of the following: (S1) A memory operand (S2) A processor register (S3)...
Machine Instructions and Addressing Modes
GATE CS 2015 Set 2, Q.52 (CS Q.42)
Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the m...
Machine Instructions and Addressing Modes
GATE CS 2014 Set 1, Q.19 (CS Q.9)
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immedi...
Machine Instructions and Addressing Modes
GATE CS 2011, Q.21 (CS Q.21)
Consider a hypothetical processor with an instruction of type
LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The...Machine Instructions and Addressing Modes