Computer Organization and Architecture · Previous year questions
I/O Interface, Interrupts and DMA
14 questions from GATE CS 2011 to 2026, newest first.
Questions
GATE CS 2026 Set 2, Q.18
Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Se...
I/O Interface, Interrupts and DMA
GATE CS 2025 Set 1, Q.11
Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously...
I/O Interface, Interrupts and DMA
GATE CS 2024 Set 1, Q.15
Which one of the following statements is FALSE?
I/O Interface, Interrupts and DMA
GATE CS 2024 Set 2, Q.11
Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which on...
I/O Interface, Interrupts and DMA
GATE CS 2024 Set 2, Q.53
Consider a disk with the following specifications: rotation speed of 6000 RPM, average seek time of 5 milliseconds, 500 sectors/track, 512-byte sectors. A file has content store...
File Systems, I/O and Disk Scheduling · I/O Interface, Interrupts and DMA
GATE CS 2023, Q.34
A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and c...
I/O Interface, Interrupts and DMA
GATE CS 2022, Q.17
Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?
I/O Interface, Interrupts and DMA
GATE CS 2021 Set 2, Q.30 (CS Q.20)
Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular interv...
I/O Interface, Interrupts and DMA
GATE CS 2020, Q.13 (CS Q.3)
Consider the following statements. I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored interrupt, the CPU does polling to...
I/O Interface, Interrupts and DMA
GATE CS 2016 Set 1, Q.41 (CS Q.31)
The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addre...
I/O Interface, Interrupts and DMA
GATE CS 2014 Set 2, Q.65 (CS Q.55)
Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nan...
I/O Interface, Interrupts and DMA
GATE CS 2013, Q.28 (CS Q.28)
Consider the following sequence of micro-operations. …
I/O Interface, Interrupts and DMA
GATE CS 2011, Q.11 (CS Q.11)
A computer handles several interrupt sources of which the following are relevant for this question. - Interrupt from CPU temperature sensor (raises interrupt if CPU temperature...
I/O Interface, Interrupts and DMA
GATE CS 2011, Q.28 (CS Q.28)
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory. ...
I/O Interface, Interrupts and DMA