GATE CS 2023 Q.42: Memory Hierarchy: Cache, Main Memory and Secondary Storage

A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high.

Four 1 KB memory blocks (X1, X2, X3, X4) with 10-bit address bus (IA11-IA5, IA2-IA0) connected to Addr and a 2-to-4 decoder driven by IA4 (A1) and IA3 (A0) connected to active-high chip select CS.

The input memory addresses (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?

(0, 1, 2, 3)

(0, 1024, 2048, 3072)

(0, 8, 16, 24)

(0, 0, 0, 0)

Official answer and solution

Official answer: C
From: Official GATE 2023 answer key

Solution

Identify the bit positions of IA4 and IA3 in the address bus to find starting addresses where Addr = 0.

The 12-bit address bus is $\text{IA}_{11}\dots\text{IA}_0$ .
The 10 address lines connected to Addr of each block are $\text{IA}_{11}\dots\text{IA}_5$ and $\text{IA}_2\dots\text{IA}_0$ . For the starting location of each block, $\text{Addr} = 0$ , meaning all these 10 lines must be $0$ .
The chip select lines are driven by the decoder inputs:
- $A_1 = \text{IA}_4$ (weight $2^4 = 16$ )
- $A_0 = \text{IA}_3$ (weight $2^3 = 8$ )
Evaluating the starting address $(\text{IA}_{11}\dots\text{IA}_0)$ $(IA_{11} \dots IA_{0})$ for each decoder output:
- For block $X_1$ ( $Q_0$ enabled): $A_1 A_0 = 00 \implies \text{IA}_4=0, \text{IA}_3=0 \implies \text{Address} = 0$
- For block $X_2$ ( $Q_1$ enabled): $A_1 A_0 = 01 \implies \text{IA}_4=0, \text{IA}_3=1 \implies \text{Address} = 2^3 = 8$
- For block $X_3$ ( $Q_2$ enabled): $A_1 A_0 = 10 \implies \text{IA}_4=1, \text{IA}_3=0 \implies \text{Address} = 2^4 = 16$
- For block $X_4$ ( $Q_3$ enabled): $A_1 A_0 = 11 \implies \text{IA}_4=1, \text{IA}_3=1 \implies \text{Address} = 16 + 8 = 24$

Thus, the starting decimal addresses are $(0, 8, 16, 24)$ .

Final answer

Option (C)

Common trap

Assuming the decoder lines are the most significant bits (which would give $0, 1024, 2048, 3072$ ).

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2023 Computer Science and Information Technology (CS)
Question: 42 of 65
Section: Computer Science and Information Technology

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