Question
Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies and such that . If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is ________ GHz, ignoring delays in the pipeline registers.
Official answer and solution
- Accepted answers
- 3.9 to 4.1
- From
- Official GATE 2016 answer key
Solution
Determine the original pipeline bottleneck stage latency from the processor frequency, then recalculate after splitting.
Given a 3-stage pipeline operating at clock frequency :
The cycle time of an unbuffered pipeline is bounded by the longest stage:
We are given the stage latency relations:
Express all stage latencies in terms of :
Clearly, is the longest stage. Therefore, the original cycle time is:
This gives:
The longest stage is split into two equal stages:
The new 4-stage pipeline has latencies .
The new cycle time is the maximum of the new stage latencies:
The new clock frequency is:
4
Assuming the new cycle time is halved ( ns, yielding GHz), forgetting that ns now becomes the new bottleneck.
The answer is the one in the official GATE answer key. The solution is this site's own explanation.
Source
- Paper
- GATE 2016 Computer Science and Information Technology (CS) Session 2
- Question
- 43 of 65, printed as CS Q.33
- Section
- Computer Science and Information Technology
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