Question

Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies τ1,τ2,\tau_1, \tau_2, and τ3\tau_3 such that τ1=3τ2/4=2τ3\tau_1 = 3\tau_2 / 4 = 2\tau_3. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is ________ GHz, ignoring delays in the pipeline registers.

Official answer and solution
Accepted answers
3.9 to 4.1
From
Official GATE 2016 answer key

Solution

Determine the original pipeline bottleneck stage latency from the processor frequency, then recalculate after splitting.

Given a 3-stage pipeline operating at clock frequency f=3 GHzf = 3\text{ GHz}:

Clock cycle time T=1f=13 GHz=13 ns\text{Clock cycle time } T = \frac{1}{f} = \frac{1}{3\text{ GHz}} = \frac{1}{3}\text{ ns}

The cycle time of an unbuffered pipeline is bounded by the longest stage:

T=max⁡(τ1,τ2,τ3)T = \max(\tau_1, \tau_2, \tau_3)

We are given the stage latency relations:

τ1=34τ2=2τ3\tau_1 = \frac{3}{4}\tau_2 = 2\tau_3

Express all stage latencies in terms of τ2\tau_2:

  • τ1=0.75τ2\tau_1 = 0.75 \tau_2
  • τ3=τ12=38τ2=0.375τ2\tau_3 = \frac{\tau_1}{2} = \frac{3}{8}\tau_2 = 0.375 \tau_2

Clearly, τ2\tau_2 is the longest stage. Therefore, the original cycle time is:

T=τ2=13 nsT = \tau_2 = \frac{1}{3}\text{ ns}

This gives:

  • τ1=34×13=14 ns=0.25 ns\tau_1 = \frac{3}{4} \times \frac{1}{3} = \frac{1}{4}\text{ ns} = 0.25\text{ ns}
  • τ3=12×14=18 ns=0.125 ns\tau_3 = \frac{1}{2} \times \frac{1}{4} = \frac{1}{8}\text{ ns} = 0.125\text{ ns}

The longest stage τ2\tau_2 is split into two equal stages:

τ2a=τ2b=τ22=1/32=16 ns≈0.167 ns\tau_{2a} = \tau_{2b} = \frac{\tau_2}{2} = \frac{1/3}{2} = \frac{1}{6}\text{ ns} \approx 0.167\text{ ns}

The new 4-stage pipeline has latencies {τ1=1/4,τ2a=1/6,τ2b=1/6,τ3=1/8}\{\tau_1 = 1/4, \tau_{2a} = 1/6, \tau_{2b} = 1/6, \tau_3 = 1/8\}.
The new cycle time is the maximum of the new stage latencies:

Tnew=max⁡(14,16,16,18)=14 nsT_{\text{new}} = \max\left(\frac{1}{4}, \frac{1}{6}, \frac{1}{6}, \frac{1}{8}\right) = \frac{1}{4}\text{ ns}

The new clock frequency is:

fnew=1Tnew=11/4 ns=4 GHzf_{\text{new}} = \frac{1}{T_{\text{new}}} = \frac{1}{1/4\text{ ns}} = 4\text{ GHz}
Final answer

4

Common trap

Assuming the new cycle time is halved (1/61/6 ns, yielding 66 GHz), forgetting that τ1=1/4\tau_1 = 1/4 ns now becomes the new bottleneck.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper
GATE 2016 Computer Science and Information Technology (CS) Session 2
Question
43 of 65, printed as CS Q.33
Section
Computer Science and Information Technology

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