Question 53

Analysis of Cache Miss Penalty:

• On a cache miss, an entire cache block (or line) must be fetched from the lower-level memory hierarchy (main memory) into the cache.
• Miss penalty consists of memory access latency plus data transfer time across the bus:
  $$\text{Miss Penalty} = \text{Latency} + \frac{\text{Block Size}}{\text{Bus Bandwidth}}.$$
• A smaller block size transfers fewer bytes on every miss, directly decreasing the transfer time and resulting in a lower miss penalty. Statement (D) is CORRECT.

Evaluating Other Options:

• (A) Incorrect: Larger block sizes (up to a reasonable threshold) better exploit spatial locality by bringing neighboring words into the cache in advance.
• (B) Incorrect: For a fixed cache capacity, a smaller block size increases the number of blocks, requiring more index/tag entries and therefore increasing total tag overhead.
• (C) Incorrect: Hit time is governed by cache access speed and comparator logic; larger tags require wider comparators and do not lower hit time.