GATE CS 2011 Q.43 (CS Q.43): Memory Hierarchy: Cache, Main Memory and Secondary Storage

An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following.

1 Valid bit
1 Modified bit
As many bits as the minimum needed to identify the memory block mapped in the cache.

What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?

4864 bits

6144 bits

6656 bits

5376 bits

Official answer and solution

Official answer: D
From: Official GATE 2011 answer key

Solution

Determine the address bit breakdown and total meta-data storage in bits for the direct-mapped cache controller.

Cache capacity = 8 KB = $2^{13}$ bytes. Block size = 32 bytes = $2^5$ bytes.

Block offset bits = $5$ bits.

Number of cache lines:

\text{Lines} = \frac{8192\text{ bytes}}{32\text{ bytes}} = 256 = 2^8\text{ lines}

Index bits = $8$ bits.

Tag bits per line in a 32-bit address:

\text{Tag bits} = 32 - \text{Index} - \text{Offset} = 32 - 8 - 5 = 19\text{ bits}

Meta-data bits per cache line:

\text{Bits per line} = 1\text{ (valid bit)} + 1\text{ (modified bit)} + 19\text{ (tag bits)} = 21\text{ bits}

Total meta-data memory for all 256 lines:

\text{Total Meta-data} = 256 \times 21\text{ bits} = 5376\text{ bits}

Final answer

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2011 Computer Science and Information Technology (CS)
Question: 43 of 65, printed as CS Q.43
Section: Computer Science and Information Technology

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