Question
A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is __________ .
Official answer and solution
- Official answer
- 160
- From
- Official GATE 2019 answer key
Solution
Calculate the total cycle time per cache block transfer and compute memory bandwidth in bytes per second.
We are given:
- Cache block size =
- Word size = , so each block is
- Clock frequency =
The cycles required to service one cache block read miss are:
- Accept starting address:
- Fetch all 8 words from memory:
- Transmit words at 1 word/cycle:
Total cycles per block miss:
The rate at which blocks can be serviced is:
The maximum bandwidth in bytes per second is:
Thus, the required value is .
160
Counting transmission as 1 cycle instead of 8 cycles (1 word per cycle for 8 words).
The answer is the one in the official GATE answer key. The solution is this site's own explanation.
Source
- Paper
- GATE 2019 Computer Science and Information Technology (CS)
- Question
- 55 of 65, printed as CS Q.45
- Section
- Computer Science and Information Technology
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