GATE CS Mastery
Cheat sheets

GATE CS 2023 · Computer Organization and Architecture

Question 33

NAT1 markNo negative markingEasy (estimate)

Question

Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.

The total execution time for executing 100 instructions on this processor is _______ ns.

Official answer and solution
Official answer
2040
From
Official GATE 2023 answer key

Solution

Determine the clock cycle time from the maximum stage delay and calculate pipeline execution time for nn instructions.

  1. The stage delays are τ1=10 ns\tau_1 = 10\text{ ns}, τ2=20 ns\tau_2 = 20\text{ ns}, τ3=14 ns\tau_3 = 14\text{ ns}. With no latch delay, the pipeline clock cycle time is:

    τ=max⁡(10,20,14)=20 ns\tau = \max(10, 20, 14) = 20\text{ ns}

  2. In a kk-stage pipeline, the number of clock cycles required to execute nn hazard-free instructions is:

    Cycles=k+(n−1)\text{Cycles} = k + (n - 1)

    For k=3k = 3 stages and n=100n = 100 instructions:

    Cycles=3+(100−1)=3+99=102 cycles\text{Cycles} = 3 + (100 - 1) = 3 + 99 = 102\text{ cycles}

  3. Total execution time:

    Time=102×20 ns=2040 ns\text{Time} = 102 \times 20\text{ ns} = 2040\text{ ns}
Final answer

2040

Common trap

Multiplying 100×20=2000 ns100 \times 20 = 2000\text{ ns}, forgetting the initial pipeline fill delay of (k−1)=2(k - 1) = 2 cycles.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper
GATE 2023 Computer Science and Information Technology (CS)
Question
33 of 65
Section
Computer Science and Information Technology

Report an error in this question

GATE questions are the work of the organising institutes. This site is independent and is not affiliated with them.