GATE CS 2015 Set 1 Q.48 (CS Q.38): Instruction Pipelining and Hazards

Consider a non-pipelined processor with a clock rate of $2.5\text{ gigahertz}$ and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to $2\text{ gigahertz}$ . Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is _____.

Your answer

Official answer and solution

Official answer: 3.2
From: Official GATE 2015 answer key

Solution

Compute instruction execution time in non-pipelined and pipelined processors to find speedup.

Non-pipelined processor:
- Clock frequency $f_1 = 2.5\text{ GHz} \implies$ Clock cycle time $\tau_1 = \frac{1}{2.5\text{ GHz}} = 0.4\text{ ns}$ .
- Average cycles per instruction $\text{CPI}_1 = 4$ .
- Execution time per instruction: $T_1 = \text{CPI}_1 \times \tau_1 = 4 \times 0.4\text{ ns} = 1.6\text{ ns}.$
Pipelined processor:
- Upgraded to 5 stages with clock frequency $f_2 = 2\text{ GHz} \implies \tau_2 = \frac{1}{2\text{ GHz}} = 0.5\text{ ns}$ .
- With no stalls, the ideal throughput is 1 instruction per cycle: $\text{CPI}_2 = 1$ .
- Effective execution time per instruction in steady state: $T_2 = 1 \times \tau_2 = 0.5\text{ ns}.$
Speedup:
$\text{Speedup} = \frac{T_1}{T_2} = \frac{1.6\text{ ns}}{0.5\text{ ns}} = 3.2.$

The speedup is $3.2$ .

Final answer

3.2

Common trap

Neglecting the clock frequency change from 2.5 GHz down to 2 GHz, which would erroneously give a speedup of 4.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2015 Computer Science and Information Technology (CS) Session 1
Question: 48 of 65, printed as CS Q.38
Section: Computer Science and Information Technology

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