Question
Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?
Official answer and solution
- Official answer
- A, B and C
- From
- Official GATE 2024 answer key
Solution
Evaluate each statement against standard 5-stage RISC pipeline forwarding (bypassing) paths and load-use hazards.
- (A) is CORRECT: Forwarding (bypassing) feeds a computed or loaded result directly from an earlier instruction's pipeline stage (EX/MEM or MEM/WB) to a later instruction's stage (such as EX) without waiting for WB.
- (B) is CORRECT: The MEM/WB pipeline register (output of the MEM stage) has a forwarding path to the ALU input multiplexers at the EX stage.
- (C) is CORRECT: Forwarding cannot eliminate all data hazard stalls - for example, a load-use data hazard (where a
LOADinstruction is immediately followed by an instruction that uses the loaded register in EX) still requires a 1-cycle pipeline stall (bubble) because the data is only available at the end of theLOAD's MEM stage. - (D) is FALSE: Forwarding requires additional hardware, including forwarding detection logic, bypass wires from pipeline registers, and larger multiplexers at the ALU inputs.
Final answer
Options (A), (B), (C)
The answer is the one in the official GATE answer key. The solution is this site's own explanation.
Source
- Paper
- GATE 2024 Computer Science and Information Technology - Set 1 (CS1)
- Question
- 30 of 65
- Section
- Computer Science and Information Technology
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