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GATE CS 2024 Set 2 · Computer Organization and Architecture

Question 11

MCQ1 markWrong answer: −1/3Easy (estimate)

Question

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

Choose one option
Official answer and solution
Official answer
C
From
Official GATE 2024 answer key

Solution

Calculate the number of DMA cycles per second (1%1\% of 4 MHz4\text{ MHz}) and multiply by the number of bits transferred per cycle (8×8=648 \times 8 = 64 bits).

  1. Processor clock frequency =4 MHz=4×106 cycles/second= 4\text{ MHz} = 4 \times 10^6\text{ cycles/second}.
  2. Number of cycles used by DMA per second (1%1\% of processor cycles):
    0.01×4×106=40,000 cycles/second0.01 \times 4 \times 10^6 = 40,000\text{ cycles/second}
  3. Data transferred per DMA cycle =8 bytes=8×8=64 bits= 8\text{ bytes} = 8 \times 8 = 64\text{ bits}.
  4. Data transfer rate in bits per second:
    40,000×64=2,560,000 bits/second (or 25,60,000)40,000 \times 64 = 2,560,000\text{ bits/second (or } 25,60,000\text{)}
Final answer

Option (C)

Common trap

Forgetting to convert 8 bytes to 64 bits (which gives 3,20,000 bytes/sec) or misplacing a factor of 10.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper
GATE 2024 Computer Science and Information Technology - Set 2 (CS2)
Question
11 of 65
Section
Computer Science and Information Technology

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