Question 24

Given parameters:

• Byte addressable main memory size $= 2^{20}\text{ bytes}$, which requires $\log_2(2^{20}) = 20$ address bits.
• Cache block (line) size $= 16\text{ bytes} = 2^4\text{ bytes}$, so the block offset takes $4$ bits.
• Direct-mapped cache has $2^{12}$ cache lines, so the cache line index takes $12$ bits.
• Tag bits $= 20 - (12 + 4) = 4$ bits.

Bit layout of a 20-bit address (5 hexadecimal digits):

• Tag: bits 19-16 (1 hexadecimal digit)
• Cache Line Index: bits 15-4 (3 hexadecimal digits)
• Block Offset: bits 3-0 (1 hexadecimal digit)

For the main memory address $(\text{E201F})_{16}$:

• The 5 hex digits are E 2 0 1 F.
• Tag $= \text{E}$
• Cache line address $= 201$
• Block offset $= \text{F}$

Thus, the tag and cache line address are E, 201 (Option A).