Question

Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.

P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.

Which processor has the highest peak clock frequency?

Choose one option
Official answer and solution
Official answer
C
From
Official GATE 2014 answer key

Solution

Find the maximum stage latency for each pipeline processor to determine its minimum clock period and maximum clock frequency.

In a synchronous pipelined processor with negligible register latency, the minimum clock cycle period TcycleT_{\text{cycle}} is bounded by the slowest (bottleneck) pipeline stage:

Tcycle=max⁡i(τi)T_{\text{cycle}} = \max_{i} (\tau_i)

and peak clock frequency is f=1Tcyclef = \frac{1}{T_{\text{cycle}}}.

Evaluating each processor:

  • P1: latencies = (1,2,2,1) ns  ⟹  T1=max⁡(1,2,2,1)=2.0 ns  ⟹  f1=12.0 ns=0.50 GHz(1, 2, 2, 1)\text{ ns} \implies T_1 = \max(1, 2, 2, 1) = 2.0\text{ ns} \implies f_1 = \frac{1}{2.0\text{ ns}} = 0.50\text{ GHz}.
  • P2: latencies = (1,1.5,1.5,1.5) ns  ⟹  T2=max⁡(1,1.5,1.5,1.5)=1.5 ns  ⟹  f2=11.5 ns≈0.67 GHz(1, 1.5, 1.5, 1.5)\text{ ns} \implies T_2 = \max(1, 1.5, 1.5, 1.5) = 1.5\text{ ns} \implies f_2 = \frac{1}{1.5\text{ ns}} \approx 0.67\text{ GHz}.
  • P3: latencies = (0.5,1,1,0.6,1) ns  ⟹  T3=max⁡(0.5,1,1,0.6,1)=1.0 ns  ⟹  f3=11.0 ns=1.00 GHz(0.5, 1, 1, 0.6, 1)\text{ ns} \implies T_3 = \max(0.5, 1, 1, 0.6, 1) = 1.0\text{ ns} \implies f_3 = \frac{1}{1.0\text{ ns}} = 1.00\text{ GHz}.
  • P4: latencies = (0.5,0.5,1,1,1.1) ns  ⟹  T4=max⁡(0.5,0.5,1,1,1.1)=1.1 ns  ⟹  f4=11.1 ns≈0.91 GHz(0.5, 0.5, 1, 1, 1.1)\text{ ns} \implies T_4 = \max(0.5, 0.5, 1, 1, 1.1) = 1.1\text{ ns} \implies f_4 = \frac{1}{1.1\text{ ns}} \approx 0.91\text{ GHz}.

The shortest clock cycle period is 1.0 ns1.0\text{ ns}, achieved by processor P3, giving the highest peak clock frequency of 1.0 GHz1.0\text{ GHz}.

This matches option C.

Final answer

C

Common trap

Averaging the stage latencies instead of finding the maximum (bottleneck) stage latency.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper
GATE 2014 Computer Science and Information Technology (CS) Session 3
Question
19 of 65, printed as CS Q.9
Section
Computer Science and Information Technology

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