Question
Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.
P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.
Which processor has the highest peak clock frequency?
Official answer and solution
- Official answer
- C
- From
- Official GATE 2014 answer key
Solution
Find the maximum stage latency for each pipeline processor to determine its minimum clock period and maximum clock frequency.
In a synchronous pipelined processor with negligible register latency, the minimum clock cycle period is bounded by the slowest (bottleneck) pipeline stage:
and peak clock frequency is .
Evaluating each processor:
- P1: latencies = .
- P2: latencies = .
- P3: latencies = .
- P4: latencies = .
The shortest clock cycle period is , achieved by processor P3, giving the highest peak clock frequency of .
This matches option C.
C
Averaging the stage latencies instead of finding the maximum (bottleneck) stage latency.
The answer is the one in the official GATE answer key. The solution is this site's own explanation.
Source
- Paper
- GATE 2014 Computer Science and Information Technology (CS) Session 3
- Question
- 19 of 65, printed as CS Q.9
- Section
- Computer Science and Information Technology
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