GATE CS 2016 Set 1 Q.42 (CS Q.32): Instruction Pipelining and Hazards

The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is _____ percent.

Your answer

Official answer and solution

Accepted answers: 33 to 34
From: Official GATE 2016 answer key

Solution

Compute original and modified clock cycle times from the bottleneck stage and find the throughput ratio.

In a synchronous pipelined processor, the clock cycle time is determined by the maximum stage delay (the bottleneck stage):

\tau = \max(\text{stage delays})

For the original 4-stage pipeline:

\tau_1 = \max(800, 500, 400, 300) = 800\text{ ps}

The original throughput is:

TP_1 = \frac{1}{\tau_1} = \frac{1}{800\text{ ps}}

The 800 ps stage is split into two stages with delays 600 ps and 350 ps. The new 5-stage pipeline has delays: 600, 350, 500, 400, and 300 ps.

\tau_2 = \max(600, 350, 500, 400, 300) = 600\text{ ps}

The new throughput is:

TP_2 = \frac{1}{\tau_2} = \frac{1}{600\text{ ps}}

The percentage increase in throughput is:

\text{Increase} = \left(\frac{TP_2 - TP_1}{TP_1}\right) \times 100\% = \left(\frac{\tau_1}{\tau_2} - 1\right) \times 100\% = \left(\frac{800}{600} - 1\right) \times 100\% = \frac{1}{3} \times 100\% \approx 33.33\%

Final answer

33.33

Common trap

Calculating the percentage decrease in cycle time ( $25\%$ ) rather than the percentage increase in throughput ( $33.33\%$ ).

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2016 Computer Science and Information Technology (CS) Session 1
Question: 42 of 65, printed as CS Q.32
Section: Computer Science and Information Technology

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