GATE CS 2024 Set 1 Q.56: Memory Hierarchy: Cache, Main Memory and Secondary Storage

A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss rate on instruction cache and 8% miss rate on data cache. The miss penalty is 100 cycles. The speedup (rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is _________

Your answer

Official answer and solution

Official answer: 3
From: Official GATE 2024 answer key

Solution

Compute the average memory stall cycles per instruction from both I-cache and D-cache misses, add to the ideal CPI, and divide by the ideal CPI.

Instruction cache stall cycles per instruction:
Every instruction ( $100\%$ ) is fetched from the instruction cache: $\text{I-cache stalls} = 1.00 \times 0.02 \times 100 = 2\text{ cycles/instruction}$
Data cache stall cycles per instruction:
Only load/store instructions ( $25\%$ ) access the data cache: $\text{D-cache stalls} = 0.25 \times 0.08 \times 100 = 2\text{ cycles/instruction}$
Effective CPI with cache misses: $\text{CPI}_{\text{actual}} = \text{CPI}_{\text{ideal}} + 2 + 2 = 2 + 4 = 6$
Speedup with a perfect cache: $\text{Speedup} = \frac{\text{CPI}_{\text{actual}}}{\text{CPI}_{\text{ideal}}} = \frac{6}{2} = 3$

Final answer

Common trap

Applying the 8% D-cache miss rate to all instructions instead of only the 25% load/store instructions.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2024 Computer Science and Information Technology - Set 1 (CS1)
Question: 56 of 65
Section: Computer Science and Information Technology

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