Memory Hierarchy: Cache, Main Memory and Secondary Storage: GATE CS previous year questions (Computer Organization and Architecture)

GATE CS 2026 Set 1MCQ2 marksEasy (estimate)
GATE CS 2026 Set 1, Q.38
The size of the physical address space of a processor is $2^{32}$ bytes. The capacity of a cache memory unit is $2^{23}$ bytes. The cache block size is $128$ bytes. The cache me...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2026 Set 2MSQ2 marksMedium (estimate)
GATE CS 2026 Set 2, Q.52
Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2026 Set 2NAT2 marksMedium (estimate)
GATE CS 2026 Set 2, Q.56
Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical addres...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2025 Set 1MCQ2 marksEasy (estimate)
GATE CS 2025 Set 1, Q.36
Consider a memory system with 1M bytes of main memory and 16K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 by...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2025 Set 1NAT2 marksEasy (estimate)
GATE CS 2025 Set 1, Q.53
A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. I...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2025 Set 2MCQ2 marksEasy (estimate)
GATE CS 2025 Set 2, Q.39
For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2025 Set 2NAT2 marksEasy (estimate)
GATE CS 2025 Set 2, Q.55
Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the "hit rate" for L1 cache is 9...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2024 Set 1MSQ2 marksEasy (estimate)
GATE CS 2024 Set 1, Q.53
Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of them use the LRU (Least Rec...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2024 Set 1NAT2 marksEasy (estimate)
GATE CS 2024 Set 1, Q.54
Consider a 512 GB hard disk with 32 storage surfaces. There are 4096 sectors per track and each sector holds 1024 bytes of data. The number of cylinders in the hard disk is ____...
Memory Hierarchy: Cache, Main Memory and Secondary Storage · File Systems, I/O and Disk Scheduling
GATE CS 2024 Set 1NAT2 marksEasy (estimate)
GATE CS 2024 Set 1, Q.56
A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss rate on instruction...
Memory Hierarchy: Cache, Main Memory and Secondary Storage · Instruction Pipelining and Hazards
GATE CS 2023MCQ2 marksMedium (estimate)
GATE CS 2023, Q.42
A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these me...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2023NAT2 marksEasy (estimate)
GATE CS 2023, Q.58
Consider a computer system with 57-bit virtual addressing using multi-level tree-structured page tables with $L$ levels for virtual to physical address translation. The page siz...
Memory Management and Virtual Memory · Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2023NAT2 marksMedium (estimate)
GATE CS 2023, Q.64
An 8-way set associative cache of size 64 KB ( $1 KB = 1024 bytes$ ) is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK O...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2022MSQ1 markMedium (estimate)
GATE CS 2022, Q.24
Let $W_{B}$ and $W_{T}$ be two set associative cache organizations that use LRU algorithm for cache block replacement. $W_{B}$ is a write back cache and $W_{T}$ is a write through cache...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2022NAT1 markMedium (estimate)
GATE CS 2022, Q.33
A cache memory that has a hit rate of 0.8 has an access latency 10 ns and miss penalty 100 ns. An optimization is done on the cache to reduce the miss rate. However, the optimiz...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2022MSQ2 marksHard (estimate)
GATE CS 2022, Q.54
Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the exe...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2021 Set 1NAT1 markEasy (estimate)
GATE CS 2021 Set 1, Q.32 (CS Q.22)
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $32 KB$ …
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2021 Set 2NAT1 markEasy (estimate)
GATE CS 2021 Set 2, Q.29 (CS Q.19)
Consider a set-associative cache of size 2KB ( $1 KB = 2^{10} bytes$ ) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32-bit addr...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2021 Set 2MCQ2 marksMedium (estimate)
GATE CS 2021 Set 2, Q.37 (CS Q.27)
Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements: $S_{1}$ : Read misses in a write through L1 cache do...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2020NAT1 markEasy (estimate)
GATE CS 2020, Q.30 (CS Q.20)
If there are $m$ input lines and $n$ output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of $m + n$ is _______.
Combinational Circuits · Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2020NAT1 markMedium (estimate)
GATE CS 2020, Q.31 (CS Q.21)
A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2020MCQ2 marksMedium (estimate)
GATE CS 2020, Q.40 (CS Q.30)
A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2019MCQ1 markEasy (estimate)
GATE CS 2019, Q.11 (CS Q.1)
A certain processor uses a fully associative cache of size $16 kB$ . The cache block size is $16 bytes$ . Assume that the main memory is byte addressable and uses a...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2019MCQ1 markEasy (estimate)
GATE CS 2019, Q.12 (CS Q.2)
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by $A_{15}$ to $A_{0}$ . What is...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2019NAT2 marksMedium (estimate)
GATE CS 2019, Q.55 (CS Q.45)
A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, t...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2018NAT1 markMedium (estimate)
GATE CS 2018, Q.33 (CS Q.23)
A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$ . The time taken to...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2018MCQ2 marksMedium (estimate)
GATE CS 2018, Q.44 (CS Q.34)
The size of the physical address space of a processor is $2^{P}$ bytes. The word length is $2^{W}$ bytes. The capacity of cache memory is $2^{N}$ bytes. The size of each cache block i...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 1NAT1 markMedium (estimate)
GATE CS 2017 Set 1, Q.25 (CS Q.25)
Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 1NAT2 marksHard (estimate)
GATE CS 2017 Set 1, Q.51 (CS Q.51)
Consider a 2-way set associative cache with 256 blocks and uses LRU replacement. Initially the cache is empty. Conflict misses are those misses which occur due to contention of...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 1NAT2 marksEasy (estimate)
GATE CS 2017 Set 1, Q.54 (CS Q.54)
A cache memory unit with capacity of $N$ words and block size of $B$ words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits....
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 2MCQ2 marksMedium (estimate)
GATE CS 2017 Set 2, Q.29 (CS Q.29)
In a two-level cache system, the access times of $L_{1}$ and $L_{2}$ caches are 1 and 8 clock cycles, respectively. The miss penalty from the $L_{2}$ cache to main memory is 18 clock...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 2NAT2 marksMedium (estimate)
GATE CS 2017 Set 2, Q.45 (CS Q.45)
The read access times and the hit ratios for different caches in a memory hierarchy are as given below. | Cache | Read access time (in nanoseconds) | Hit ratio | | :--- | :---:...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2017 Set 2NAT2 marksEasy (estimate)
GATE CS 2017 Set 2, Q.53 (CS Q.53)
Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used w...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2016 Set 2NAT2 marksMedium (estimate)
GATE CS 2016 Set 2, Q.42 (CS Q.32)
The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is ________ bits.
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2016 Set 2NAT2 marksMedium (estimate)
GATE CS 2016 Set 2, Q.60 (CS Q.50)
A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is 1 ms and to read a b...
File Systems, I/O and Disk Scheduling · Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2015 Set 1NAT2 marksEasy (estimate)
GATE CS 2015 Set 1, Q.58 (CS Q.48)
Consider a disk pack with a seek time of $4$ milliseconds and rotational speed of $10000$ rotations per minute (RPM). It has $600$ sectors per track and each sector can store…
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2015 Set 2NAT1 markEasy (estimate)
GATE CS 2015 Set 2, Q.34 (CS Q.24)
Assume that for a certain processor, a read request takes 50 nanoseconds on a cache miss and 5 nanoseconds on a cache hit. Suppose while running a program, it was observed that...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2015 Set 3MCQ1 markEasy (estimate)
GATE CS 2015 Set 3, Q.24 (CS Q.14)
Consider a machine with a byte addressable main memory of $2^{20}$ bytes, block size of 16 bytes and a direct mapped cache having $2^{12}$ cache lines. Let the addresses of two...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2015 Set 3MCQ2 marksMedium (estimate)
GATE CS 2015 Set 3, Q.40 (CS Q.30)
Consider the following two C code segments. $Y$ and $X$ are one and two dimensional arrays of size $n$ and $n \times n$ respectively, where $2 \leq n \leq 10$ . Assume that in both...
Pointers, Arrays and Strings · Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2014 Set 1MCQ2 marksMedium (estimate)
GATE CS 2014 Set 1, Q.54 (CS Q.44)
An access sequence of cache block addresses is of length $N$ and contains $n$ unique block addresses. The number of unique block addresses between two consecutive accesses to th...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2014 Set 2NAT1 markMedium (estimate)
GATE CS 2014 Set 2, Q.19 (CS Q.9)
A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2014 Set 2MCQ2 marksEasy (estimate)
GATE CS 2014 Set 2, Q.53 (CS Q.43)
In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2014 Set 2MCQ2 marksMedium (estimate)
GATE CS 2014 Set 2, Q.54 (CS Q.44)
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2014 Set 3NAT2 marksMedium (estimate)
GATE CS 2014 Set 3, Q.54 (CS Q.44)
The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation wit...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2013MCQ1 markEasy (estimate)
GATE CS 2013, Q.20 (CS Q.20)
In a $k$ -way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lin...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2013MCQ2 marksMedium (estimate)
GATE CS 2013, Q.46 (CS Q.46)
A RAM chip has a capacity of 1024 words of 8 bits each ( $1 K \times 8$ ). The number of $2 \times 4$ decoders with enable line needed to construct a $16 K \times 16$ ...
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2013MCQ2 marksMedium (estimate)
GATE CS 2013, Q.53 (CS Q.53)
What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer?
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2012MCQ2 marksEasy (estimate)
GATE CS 2012, Q.54 (CS Q.54)
The number of bits in the tag field of an address is
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2012MCQ2 marksMedium (estimate)
GATE CS 2012, Q.55 (CS Q.55)
The size of the cache tag directory is
Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2011MCQ2 marksMedium (estimate)
GATE CS 2011, Q.43 (CS Q.43)
An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag in...
Memory Hierarchy: Cache, Main Memory and Secondary Storage

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