GATE CS 2018 Q.33 (CS Q.23): Memory Hierarchy: Cache, Main Memory and Secondary Storage

A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$ . The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.

Your answer

Official answer and solution

Accepted answers: 59 to 60
From: Official GATE 2018 answer key

Solution

Calculate the time required to refresh all rows in a refresh period, then subtract refresh overhead from total time.

DRAM refresh occurs across all memory chips simultaneously on a row-by-row basis.
The number of rows to refresh in each DRAM chip is $2^{14} = 16384$ rows.

Each refresh operation takes $50\text{ ns}$ . Total time required to refresh all rows is:

T_{\text{refresh}} = 16384 \times 50\text{ ns} = 819,200\text{ ns} = 0.8192\text{ ms}

The refresh period is $2\text{ ms}$ .
The fraction of time consumed by refresh operations is:

\text{Refresh fraction} = \frac{0.8192\text{ ms}}{2.0\text{ ms}} = 0.4096 = 40.96\%

The percentage of time available for performing read/write operations is:

100\% - 40.96\% = 59.04\%

Rounding to the closest integer gives 59% (official answer key accepts 59.0 to 60.0).

Final answer

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2018 Computer Science and Information Technology (CS)
Question: 33 of 65, printed as CS Q.23
Section: Computer Science and Information Technology

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