GATE CS 2016 Set 2 Q.20 (CS Q.10): Machine Instructions and Addressing Modes

A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is ________.

Your answer

Official answer and solution

Official answer: 16
From: Official GATE 2016 answer key

Solution

Calculate the bits required for opcode and register specifiers, then subtract from the 32-bit instruction length.

Instruction word format:

\text{Instruction (32 bits)} = [\text{Opcode}] + [\text{Register 1}] + [\text{Register 2}] + [\text{Immediate Operand}]

Calculate the bit width of each component:

Opcode field: The processor has 40 distinct instructions.
$\text{Bits for Opcode} = \lceil \log_2 40 \rceil = 6 \text{ bits} \quad (2^5 = 32 < 40 \le 64 = 2^6)$
Register fields: The processor has 24 general purpose registers.
$\text{Bits per Register} = \lceil \log_2 24 \rceil = 5 \text{ bits} \quad (2^4 = 16 < 24 \le 32 = 2^5)$
For two register operands: $2 \times 5 = 10$ bits.

Remaining bits for immediate operand:

\text{Immediate field bits} = 32 - (6 + 10) = 32 - 16 = 16 \text{ bits}

Therefore, 16 bits are available for the immediate operand field.

Final answer

Common trap

Using floor instead of ceiling for logarithmic bit requirements, giving 5 bits for opcode instead of 6.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2016 Computer Science and Information Technology (CS) Session 2
Question: 20 of 65, printed as CS Q.10
Section: Computer Science and Information Technology

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