Question 45

1. Determine the clock cycle time:
   Each stage delay must be added to the buffer delay of 1 ns:

   • FI: $5 + 1 = 6\text{ ns}$
   • DI: $7 + 1 = 8\text{ ns}$
   • FO: $10 + 1 = 11\text{ ns}$
   • EI: $8 + 1 = 9\text{ ns}$
   • WO: $6 + 1 = 7\text{ ns}$
     The clock cycle duration is the maximum stage latency:
   $$T_{\text{cycle}} = \max(6, 8, 11, 9, 7) = 11\text{ ns}$$

2. Analyze the pipeline execution with branch:

   • There are 12 instructions $I_1, I_2, \dots, I_{12}$.
   • $I_4$ is a branch instruction to target $I_9$.
   • Without branch prediction, the branch outcome is determined during the Execute Instruction (EI) stage of $I_4$.
   • Cycle trace for $I_4$:
     • Cycle 4: $I_4$ is fetched (FI).
     • Cycle 5: $I_4$ is decoded (DI).
     • Cycle 6: $I_4$ operand fetch (FO).
     • Cycle 7: $I_4$ execution (EI). The branch target $I_9$ is resolved at the end of cycle 7.
   • Meanwhile, instructions $I_1, I_2, I_3$ complete normally:
     • $I_1$ finishes WO at cycle 5.
     • $I_2$ finishes WO at cycle 6.
     • $I_3$ finishes WO at cycle 7.
     • $I_4$ finishes WO at cycle 8.
   • Because the branch is taken, the target instruction $I_9$ can only be fetched starting at cycle 8.
   • The instructions executed following the branch are $I_9, I_{10}, I_{11}, I_{12}$ (a sequence of 4 instructions).
   • In an empty 5-stage pipeline, executing 4 instructions requires:
     $$5 + (4 - 1) = 8\text{ cycles}$$
   • These 8 cycles take place from cycle 8 through cycle $7 + 8 = 15$.
   • Thus, instruction $I_{12}$ finishes at the end of cycle 15.

3. Compute total time:

   $$\text{Total time} = 15 \times 11\text{ ns} = 165\text{ ns}$$

This matches option (B).