Computer Organization and Architecture · Previous year questions
Instruction Pipelining and Hazards
30 questions from GATE CS 2011 to 2026, newest first.
Questions
GATE CS 2026 Set 1, Q.16
Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?
Instruction Pipelining and Hazards
GATE CS 2026 Set 1, Q.60
The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let denot...
Instruction Pipelining and Hazards
GATE CS 2026 Set 2, Q.57
A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performa...
Instruction Pipelining and Hazards
GATE CS 2025 Set 2, Q.56
A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that th...
Instruction Pipelining and Hazards
GATE CS 2025 Set 2, Q.61
An application executes number of instructions in 6.3 seconds. There are four types of instructions, the details of which are given in the table. The duration...
ALU, Datapath and Control Unit · Instruction Pipelining and Hazards
GATE CS 2024 Set 1, Q.30
Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the...
Instruction Pipelining and Hazards
GATE CS 2024 Set 1, Q.55
The baseline execution time of a program on a 2 GHz single core machine is 100 nanoseconds (ns). The code corresponding to 90% of the execution time can be fully parallelized. T...
Instruction Pipelining and Hazards · Calculus
GATE CS 2024 Set 1, Q.56
A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss rate on instruction...
Memory Hierarchy: Cache, Main Memory and Secondary Storage · Instruction Pipelining and Hazards
GATE CS 2024 Set 2, Q.31
An instruction format has the following structure:
Instruction Number: Opcode destination reg, source reg-1, source reg-2Consider the following sequence of instructions to be...Instruction Pipelining and Hazards
GATE CS 2024 Set 2, Q.58
A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a...
Instruction Pipelining and Hazards
GATE CS 2023, Q.33
Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is n...
Instruction Pipelining and Hazards
GATE CS 2022, Q.61
A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given pr...
Instruction Pipelining and Hazards
GATE CS 2021 Set 1, Q.63 (CS Q.53)
A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each. The...
Instruction Pipelining and Hazards
GATE CS 2021 Set 2, Q.63 (CS Q.53)
Consider a pipelined processor with 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline...
Instruction Pipelining and Hazards
GATE CS 2020, Q.53 (CS Q.43)
Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Over...
Instruction Pipelining and Hazards
GATE CS 2020, Q.54 (CS Q.44)
A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name...
Instruction Pipelining and Hazards · Number Representations and Computer Arithmetic
GATE CS 2018, Q.60 (CS Q.50)
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback...
Instruction Pipelining and Hazards
GATE CS 2017 Set 1, Q.50 (CS Q.50)
Instruction execution in a processor is divided into 5 stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stag...
Instruction Pipelining and Hazards
GATE CS 2016 Set 1, Q.42 (CS Q.32)
The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design invo...
Instruction Pipelining and Hazards
GATE CS 2016 Set 2, Q.43 (CS Q.33)
Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies and such that . If the longest...
Instruction Pipelining and Hazards
GATE CS 2015 Set 1, Q.48 (CS Q.38)
Consider a non-pipelined processor with a clock rate of and average cycles per instruction of four. The same processor is upgraded to a pipelined processo...
Instruction Pipelining and Hazards
GATE CS 2015 Set 2, Q.54 (CS Q.44)
Consider the sequence of machine instructions given below: MUL R5, R0, R1 DIV R6, R2, R3 ADD R7, R5, R6 SUB R8, R7, R4 In the above sequence, R0 to R8 are general purpose regist...
Instruction Pipelining and Hazards
GATE CS 2015 Set 3, Q.57 (CS Q.47)
Consider the following code sequence having five instructions to . Each of these instructions has the following format.
OP Ri, Rj, Rkwhere operationOPis perfor...Instruction Pipelining and Hazards
GATE CS 2015 Set 3, Q.61 (CS Q.51)
Consider the following reservation table for a pipeline having three stages and : Stage \ Time 1 2 3 4 5 S1 X X S2 X X S3 X The minimum average latency (MAL) is...
Instruction Pipelining and Hazards
GATE CS 2014 Set 1, Q.53 (CS Q.43)
Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on...
Instruction Pipelining and Hazards
GATE CS 2014 Set 3, Q.19 (CS Q.9)
Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 n...
Instruction Pipelining and Hazards
GATE CS 2014 Set 3, Q.53 (CS Q.43)
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and regi...
Instruction Pipelining and Hazards
GATE CS 2013, Q.45 (CS Q.45)
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) an...
Instruction Pipelining and Hazards
GATE CS 2012, Q.20 (CS Q.20)
Register renaming is done in pipelined processors
Instruction Pipelining and Hazards · Instruction Pipelining and Hazards
GATE CS 2011, Q.41 (CS Q.41)
Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end...
Instruction Pipelining and Hazards