GATE CS 2017 Set 1 Q.9 (CS Q.9): ALU, Datapath and Control Unit

When two 8-bit numbers $A_7 \dots A_0$ and $B_7 \dots B_0$ in 2's complement representation (with $A_0$ and $B_0$ as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are $S_7 \dots S_0$ and the carry bits are $C_7 \dots C_0$ . An overflow is said to have occurred if

the carry bit $C_7$ is 1

all the carry bits $(C_7, \dots, C_0)$ are 1

$(A_7 B_7 \overline{S_7} + \overline{A_7} \, \overline{B_7} S_7)$ is 1

$(A_0 B_0 \overline{S_0} + \overline{A_0} \, \overline{B_0} S_0)$ is 1

Official answer and solution

Official answer: C
From: Official GATE 2017 answer key

Solution

Formulate the arithmetic overflow condition for 2's complement addition based on operand signs and the result sign.

In 2's complement representation, the most significant bit (MSB) is the sign bit: 0 indicates a non-negative number and 1 indicates a negative number. Here, the MSBs are $A_7, B_7$ for the operands and $S_7$ for the sum.

Overflow can only occur when adding two numbers of the same sign:

Adding two negative numbers ( $A_7 = 1, B_7 = 1$ ) yields a positive result ( $S_7 = 0$ ). This condition is represented by the Boolean product term $A_7 B_7 \overline{S_7}$ .
Adding two non-negative numbers ( $A_7 = 0, B_7 = 0$ ) yields a negative result ( $S_7 = 1$ ). This condition is represented by the Boolean product term $\overline{A_7} \, \overline{B_7} S_7$ .

Therefore, overflow occurs if and only if:

V = A_7 B_7 \overline{S_7} + \overline{A_7} \, \overline{B_7} S_7 = 1

This matches Option C.

Final answer

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2017 Computer Science and Information Technology (CS) Session 1
Question: 9 of 65, printed as CS Q.9
Section: Computer Science and Information Technology

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