Question 54

Cache Parameters:

• Let cache capacity be $C$ bytes, block size be $B$ bytes, and set associativity be $P$ ways.
• Total blocks in cache $N = \frac{C}{B}$ (constant).
• Number of sets $S = \frac{N}{P}$.

Doubling Associativity ($P' = 2P$):

• Number of sets is halved: $S' = \frac{N}{2P} = \frac{S}{2}$.
• Set index bits $= \log_2(S') = \log_2(S) - 1$ decreases by 1 bit $\implies$ Width of set index decoder changes.
• Block offset bits $= \log_2(B)$ remains unchanged.
• Tag bits $= \text{Address bits} - \text{Index bits} - \text{Offset bits}$ increases by 1 bit $\implies$ Width of tag comparator changes.
• Number of ways per set doubles to $2P$ $\implies$ Width of way selection multiplexor changes (from $P$-to-1 to $2P$-to-1).

System Bus Width:

• The data bus between the processor/cache subsystem and main memory is determined by external system bus architecture and physical memory module widths.
• Internal cache organization (associativity) has no impact on this bus width. Thus, the width of the processor to main memory data bus is guaranteed to be NOT affected (Option D).