Question
Instruction execution in a processor is divided into 5 stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated:
(i) a naive pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.
The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is ______.
Official answer and solution
- Accepted answers
- 1.49 to 1.52
- From
- Official GATE 2017 answer key
Solution
Compute the cycle time and total execution time for 20 instructions in both naive (NP) and efficient (EP) pipelines to determine speedup.
- Naive Pipeline (NP):
- Stages: IF (5 ns), ID (4 ns), OF (20 ns), EX (10 ns), WB (3 ns).
- Number of stages .
- Buffer delay .
- Clock cycle time .
- Execution time for instructions:
- Efficient Pipeline (EP):
- The OF stage is split into OF1 (12 ns) and OF2 (8 ns).
- Stages: IF (5 ns), ID (4 ns), OF1 (12 ns), OF2 (8 ns), EX (10 ns), WB (3 ns).
- Number of stages .
- Clock cycle time .
- Execution time for instructions:
- Speedup achieved by EP over NP:
1.51
The answer is the one in the official GATE answer key. The solution is this site's own explanation.
Source
- Paper
- GATE 2017 Computer Science and Information Technology (CS) Session 1
- Question
- 50 of 65, printed as CS Q.50
- Section
- Computer Science and Information Technology
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