GATE CS 2012 Q.54 (CS Q.54): Memory Hierarchy: Cache, Main Memory and Secondary Storage

Linked answer questions

Statement for Linked Answer Questions 54 and 55:

A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.

Shared with question 55.

The number of bits in the tag field of an address is

Official answer and solution

Official answer: C
From: Official GATE 2012 answer key

Solution

Partition the 32-bit physical address into byte offset, set index, and tag bits.

Cache parameters:

Total cache data size = $256\text{ KB} = 2^{18}\text{ Bytes}$ .
Block size = $32\text{ Bytes} = 2^5\text{ Bytes}$ .
Block offset bits = $\log_2(32) = 5\text{ bits}$ .

Total cache lines:

\text{Total lines} = \frac{256\text{ KB}}{32\text{ B}} = \frac{2^{18}}{2^5} = 2^{13} = 8192\text{ lines}

Set index bits:

4-way set associative ( $P = 4 = 2^2$ lines per set).

\text{Number of sets} = \frac{2^{13}}{2^2} = 2^{11} = 2048\text{ sets}

Set index bits = $\log_2(2048) = 11\text{ bits}$ .

Tag field bits:

Total address size = 32 bits.

\text{Tag bits} = 32 - (11 + 5) = 32 - 16 = 16\text{ bits}

This confirms option (C).

Final answer

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2012 Computer Science and Information Technology (CS)
Question: 54 of 65, printed as CS Q.54
Section: Computer Science and Information Technology

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