GATE CS 2019 Q.12 (CS Q.2): Memory Hierarchy: Cache, Main Memory and Secondary Storage

The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by $A_{15}$ to $A_0$ . What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

Logic diagram showing a 5-input AND gate with inputs A15, A14, inverted A13, inverted A12, and A11, generating chip select signal CS

C800 to CFFF

CA00 to CAFF

C800 to C8FF

DA00 to DFFF

Official answer and solution

Official answer: A
From: Official GATE 2019 answer key

Solution

Determine the logic condition that asserts the chip select signal CS from the 16-bit address lines.

The circuit shows an active-high chip select signal $\text{CS}$ driven by a 5-input AND gate with inputs from address lines $A_{15}, A_{14}, A_{13}, A_{12}, A_{11}$ .

Inversion bubbles are present on the lines for $A_{13}$ and $A_{12}$ . Therefore, the output $\text{CS}$ is $1$ if and only if:

A_{15} = 1, \quad A_{14} = 1, \quad A_{13} = 0, \quad A_{12} = 0, \quad A_{11} = 1

The remaining 11 address lines $A_{10}$ through $A_0$ are not connected to the chip select logic and can take any value from $0$ to $1$ .

Converting to hexadecimal:

The most significant 5 bits are $11001_2$ .
When $A_{10} \dots A_0 = 000\,0000\,0000_2$ : $1100\,1000\,0000\,0000_2 = \text{0xC800}$
When $A_{10} \dots A_0 = 111\,1111\,1111_2$ : $1100\,1111\,1111\,1111_2 = \text{0xCFFF}$

Thus, the enabled address range is $\text{C800 to CFFF}$ .

Final answer

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2019 Computer Science and Information Technology (CS)
Question: 12 of 65, printed as CS Q.2
Section: Computer Science and Information Technology

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