Question 13

Statement I: 'Daisy chaining is used to assign priorities in attending interrupts.' In daisy chaining, interrupt acknowledge (INTA) signal propagates serially through devices in order of priority; the device closest to the CPU has highest priority. Hence, Statement I is TRUE.

Statement II: 'When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.' In a vectored interrupt, the interrupting device directly places its interrupt vector address on the data bus, so no polling is needed. Hence, Statement II is FALSE.

Statement III: 'In polling, the CPU periodically checks the status bits to know if any device needs its attention.' This is the exact definition of programmed/polled I/O. Hence, Statement III is TRUE.

Statement IV: 'During DMA, both the CPU and DMA controller can be bus masters at the same time.' A system bus can have only one bus master controlling it at any instant to prevent bus contention. When DMA is active, the CPU relinquishes the bus. Hence, Statement IV is FALSE.

Thus, only statements I and III are TRUE.