GATE CS 2011 Q.41 (CS Q.41): Instruction Pipelining and Hazards

Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.

Four-stage instruction pipeline S1 delay 5ns, S2 delay 6ns, S3 delay 11ns, S4 delay 8ns with pipeline registers delay 1ns between stages and after S4

What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?

4.0

2.5

1.1

3.0

Official answer and solution

Official answer: B
From: Official GATE 2011 answer key

Solution

Calculate non-pipelined total latency versus pipelined clock cycle period to determine speedup.

For the non-pipelined implementation, an instruction traverses all combinational stages in a single unclocked path. Total non-pipelined delay is:

T_{\text{non-pipe}} = 5\text{ ns} + 6\text{ ns} + 11\text{ ns} + 8\text{ ns} = 30\text{ ns}

For the pipelined implementation, the clock period $T_{\text{pipe}}$ is governed by the slowest stage delay plus the register delay:

T_{\text{pipe}} = \max(5, 6, 11, 8) + 1\text{ ns} = 11 + 1 = 12\text{ ns}

Under ideal conditions in steady state, one instruction completes every clock cycle ( $12\text{ ns}$ ). The speedup is:

\text{Speedup} = \frac{T_{\text{non-pipe}}}{T_{\text{pipe}}} = \frac{30\text{ ns}}{12\text{ ns}} = 2.5

Final answer

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2011 Computer Science and Information Technology (CS)
Question: 41 of 65, printed as CS Q.41
Section: Computer Science and Information Technology

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