GATE CS 2020 Q.14 (CS Q.4): ALU, Datapath and Control Unit

Consider the following data path diagram.

Single bus CPU data path architecture diagram showing MAR, MDR, IR, PC, general registers R0 through R7, temporary registers TEMP1 and TEMP2, and ALU — Single bus CPU data path architecture

Consider an instruction: $\text{R0} \leftarrow \text{R1} + \text{R2}$ . The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.

$\text{R2}_r, \text{TEMP1}_r, \text{ALU}_{\text{add}}, \text{TEMP2}_w$
$\text{R1}_r, \text{TEMP1}_w$
$\text{PC}_r, \text{MAR}_w, \text{MEM}_r$
$\text{TEMP2}_r, \text{R0}_w$
$\text{MDR}_r, \text{IR}_w$

Which one of the following is the correct order of execution of the above steps?

2, 1, 4, 5, 3

1, 2, 4, 3, 5

3, 5, 2, 1, 4

3, 5, 1, 2, 4

Official answer and solution

Official answer: C
From: Official GATE 2020 answer key

Solution

Trace the micro-operations of instruction fetch and instruction execution on the single-bus data path.

Executing an instruction consists of two major phases: Instruction Fetch and Instruction Execution.

Phase 1: Instruction Fetch

The program counter PC must first be sent to the memory address register MAR, and memory read initiated: $\text{PC}_r, \text{MAR}_w, \text{MEM}_r$ (Step 3).
When memory returns the instruction into MDR, it is loaded into the instruction register IR: $\text{MDR}_r, \text{IR}_w$ (Step 5).

Phase 2: Instruction Execution for $\text{R0} \leftarrow \text{R1} + \text{R2}$

In a single-bus architecture, the ALU needs two inputs but the bus can only carry one value at a time. Therefore, one operand must first be buffered into temporary register TEMP1: $\text{R1}_r, \text{TEMP1}_w\text{ (Step 2)}$
Next, the second operand R2 is placed on the bus, and ALU performs addition with TEMP1, storing the result in TEMP2: $\text{R2}_r, \text{TEMP1}_r, \text{ALU}_{\text{add}}, \text{TEMP2}_w\text{ (Step 1)}$
Finally, the result stored in TEMP2 is transferred via the bus into destination register R0: $\text{TEMP2}_r, \text{R0}_w\text{ (Step 4)}$

Combining the fetch and execute phases yields the sequence: 3, 5, 2, 1, 4.

Final answer

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2020 Computer Science and Information Technology (CS)
Question: 14 of 65, printed as CS Q.4
Section: Computer Science and Information Technology

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