GATE CS 2017 Set 1 Q.49 (CS Q.49): Machine Instructions and Addressing Modes

Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence:

\begin{array}{ll} \text{Instr. No.} & \text{Instruction} \\ i & \text{add R2, R3, R4} \\ i+1 & \text{sub R5, R6, R7} \\ i+2 & \text{cmp R1, R9, R10} \\ i+3 & \text{beq R1, Offset} \end{array}

If the target of the branch instruction is $i$ , then the decimal value of the Offset is ______.

Your answer

Official answer and solution

Official answer: -16
From: Official GATE 2017 answer key

Solution

Calculate the PC-relative byte offset from the next instruction address to the target branch address.

Each instruction is 4 bytes long. Let $A$ be the memory address of instruction $i$ .

The addresses of the instructions in sequence are:

Address of instruction $i$ : $A$
Address of instruction $i+1$ : $A + 4$
Address of instruction $i+2$ : $A + 8$
Address of instruction $i+3$ (beq R1, Offset): $A + 12$

The next instruction in sequence is at address $(A + 12) + 4 = A + 16$ .

The PC-relative offset is defined with respect to the address of the next instruction:

\text{Target Address} = \text{Address}(\text{Next Instruction}) + \text{Offset}

Here, the target instruction is instruction $i$ at address $A$ . Therefore:

A = (A + 16) + \text{Offset} \implies \text{Offset} = A - (A + 16) = -16

Final answer

-16.0

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2017 Computer Science and Information Technology (CS) Session 1
Question: 49 of 65, printed as CS Q.49
Section: Computer Science and Information Technology

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