GATE CS 2011 Q.28 (CS Q.28): I/O Interface, Interrupts and DMA

On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.

Initialize the address register
Initialize the count to 500
LOOP: Load a byte from device
      Store in memory at address given by address register
      Increment the address register
      Decrement the count
      If count != 0 go to LOOP

Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?

3.4

4.4

5.1

6.7

Official answer and solution

Official answer: A
From: Official GATE 2011 answer key

Solution

Compute total clock cycles required for transferring 500 bytes using the ISR program versus the DMA controller, and compute speedup.

For the Interrupt Service Routine (ISR) approach:

Initialization: Initialize address register (1 cycle) + Initialize count (1 cycle) = 2 cycles.
Each loop iteration contains:
- Load a byte from device (load-store: 2 cycles)
- Store in memory (load-store: 2 cycles)
- Increment address register (1 cycle)
- Decrement count (1 cycle)
- If count != 0 go to LOOP (1 cycle)
- Total per iteration = $2 + 2 + 1 + 1 + 1 = 7$ clock cycles.
For 500 bytes: $500 \times 7 = 3500$ cycles.
Total execution time $T_{\text{ISR}} = 2 + 3500 = 3502$ clock cycles.

For the DMA controller approach:

DMA controller initialization overhead = 20 clock cycles.
DMA transfer time = $500 \times 2 = 1000$ clock cycles.
Total execution time $T_{\text{DMA}} = 20 + 1000 = 1020$ clock cycles.

The speedup achieved by the DMA controller is:

\text{Speedup} = \frac{T_{\text{ISR}}}{T_{\text{DMA}}} = \frac{3502}{1020} \approx 3.433 \approx 3.4

Final answer

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2011 Computer Science and Information Technology (CS)
Question: 28 of 65, printed as CS Q.28
Section: Computer Science and Information Technology

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