CO · Short notes
14 short notes in syllabus order, about 122 minutes to read end to end.
A machine instruction is a bit pattern that the processor decodes and executes: it names an operation (the opcode) and the operands the operation uses. The instruction set architecture (ISA) is the full list of instructions, their formats, the registers and the memory model a programmer can rely on.
An addressing mode is the rule that turns the operand field of an instruction into the operand itself. Most modes first compute an effective address (EA), the memory address where the operand lives, and then read or write that location.
The arithmetic logic unit (ALU) is the combinational block of the datapath that performs integer arithmetic (add, subtract, compare), bitwise logic (AND, OR, XOR, NOT) and shifts on two operands, under the control of a function-select input, and reports the outcome in condition flags.
The datapath is the part of the processor that holds and moves data: the registers, the ALU, the internal buses and the connections to memory.
A hardwired control unit generates the processor's control signals with fixed combinational logic driven by a step counter.
A microprogrammed control unit stores the control signals for every step of every instruction as words in a control memory (control store).
No single memory technology is at once fast, large and cheap. Static RAM is fast but costly per bit, DRAM is slower but dense, and magnetic disks and flash are slower again but cheaper still.
Memory interfacing is the design of the connection between a processor and its main memory: how chips are combined into a memory of the required size and word width, how each address selects exactly one location, and how the memory is organised for speed.
A cache is a small, fast memory between the processor and main memory that holds copies of recently used blocks (also called lines) of main memory. The processor sends every address to the cache first.
A cache holds far fewer blocks than main memory, so many memory blocks must share each cache location. The mapping function decides where a memory block may be placed, and therefore how the cache finds it again.
An I/O interface (device controller, I/O module) connects a peripheral to the system bus. It contains a few registers that the processor reads and writes: a data register, a status register (ready, busy, error) and a control register (commands, interrupt enable).
Direct memory access (DMA) lets an I/O interface move a block of data between a device and main memory without the processor handling each word.
Pipelining overlaps the execution of several instructions, the way an assembly line overlaps the building of several cars. The work of one instruction is cut into k stages (for example fetch, decode, execute, memory access, write back).
A hazard is a situation in which the next instruction in a pipeline cannot execute in its planned clock cycle without giving a wrong result. The pipeline must then either wait (a stall, also called a bubble) or use extra hardware that removes the conflict.
