Hardwired Control Unit: short notes (Computer Organization & Architecture)

Introduction

A hardwired control unit generates the processor's control signals with fixed combinational logic driven by a step counter. For each instruction, the datapath needs a particular set of signals in step 1, another in step 2, and so on (the control sequence); a hardwired unit turns those tables into logic equations of the form "signal = OR of (step AND instruction AND condition)" and builds them directly in gates. It is in effect a finite state machine whose states are the control steps.

GATE asks you to write the logic expression for a control signal from given control sequences, to size the step counter and decoders, to count the flip-flops a control FSM needs, and to compare hardwired with microprogrammed control. The control sequences themselves come from CPU Datapath and Instruction Cycle.

Prerequisites

CPU Datapath and Instruction Cycle: the control steps and signals of each instruction.
Sequential Circuit Design and Finite State Machines: counters, state encoding and next-state logic.

Core concepts

Building blocks

Block	Input	Output
Control step counter	Clock; Reset (from End); Run (held at 0 during WMFC)	Step number in binary
Step decoder	Counter value ( $k$ bits)	One-hot step lines $T_1, T_2, \ldots$
Instruction decoder	Opcode field of IR	One line per instruction (ADD, BR, ...)
Encoder (control logic)	Step lines, instruction lines, condition codes, external inputs (MFC, interrupt request)	Every control signal

The counter advances one step per clock. The signal End resets it to step 1, starting the next fetch. While the processor waits for memory, Run is 0 and the counter holds its value; MFC sets Run again.

Control signal equations

A signal $X$ is active in step $T_i$ for instruction $I$ if the control sequence of $I$ lists $X$ in step $i$ . Fetch steps are the same for every instruction, so they appear without an instruction term:

X = \sum_{\text{fetch steps } i \text{ using } X} T_i \; + \sum_{(i,\, I) \text{ using } X} T_i \cdot I \; (\cdot \text{ condition}).

This is a sum of products: an AND gate per term and one OR gate per signal.

As a finite state machine

Each (instruction, step) pair is a state. With $S$ states, binary encoding needs $\lceil \lg S \rceil$ flip-flops and next-state logic; one-hot encoding needs $S$ flip-flops but almost no decoding. The step-counter design above is a compact encoding where the state is (opcode in IR, step count).

Hardwired against microprogrammed

Aspect	Hardwired	Microprogrammed
Signal generation	Logic gates	Words read from a control memory
Speed	Faster (gate delays only)	Slower (control memory access each step)
Changing the instruction set	Redesign the logic	Rewrite the microprogram
Complexity for large ISAs	Grows quickly, irregular	Regular, easier to design and debug
Typical use	RISC processors	CISC processors, emulation

How it works

Hardwired control: step counter, step decoder, instruction decoder and encoder — Figure 1. Hardwired control unit: the clock drives a control step counter whose value a step decoder turns into lines $T_1$ to $T_n$ ; the IR feeds an instruction decoder; an encoder combines the step lines, instruction lines, condition codes and external inputs into the control signals, and End resets the counter.

Worked derivation

Using the single-bus control sequences of CPU Datapath and Instruction Cycle:

Step	Fetch (all instructions)	ADD R1, R2, R3 (ADDR)	ADD R1, (R3) (ADDM)	BR offset (BR)
1	PC $_{out}$ , MAR $_{in}$ , Read, Select4, Add, Z $_{in}$
2	Z $_{out}$ , PC $_{in}$ , Y $_{in}$ , WMFC
3	MDR $_{out}$ , IR $_{in}$
4		R2 $_{out}$ , Y $_{in}$	R3 $_{out}$ , MAR $_{in}$ , Read	Offset $_{out}$ , SelectY, Add, Z $_{in}$
5		R3 $_{out}$ , SelectY, Add, Z $_{in}$	R1 $_{out}$ , Y $_{in}$ , WMFC	Z $_{out}$ , PC $_{in}$ , End
6		Z $_{out}$ , R1 $_{in}$ , End	MDR $_{out}$ , SelectY, Add, Z $_{in}$
7			Z $_{out}$ , R1 $_{in}$ , End

For BR, Y still holds the updated PC from step 2, so step 4 adds the offset field of IR to it. Reading down the columns:

$Z_{in} = T_1 + T_5 \cdot \text{ADDR} + T_6 \cdot \text{ADDM} + T_4 \cdot \text{BR}$
$Z_{out} = T_2 + T_6 \cdot \text{ADDR} + T_7 \cdot \text{ADDM} + T_5 \cdot \text{BR}$
$Y_{in} = T_2 + T_4 \cdot \text{ADDR} + T_5 \cdot \text{ADDM}$
$\text{End} = T_6 \cdot \text{ADDR} + T_7 \cdot \text{ADDM} + T_5 \cdot \text{BR}$
$\text{MAR}_{in} = \text{Read} = T_1 + T_4 \cdot \text{ADDM}$
$\text{PC}_{in} = T_2 + T_5 \cdot \text{BR}$
$\text{WMFC} = T_2 + T_5 \cdot \text{ADDM}$

Conditional branch. For BRN (branch if negative), step 4 is the same as for BR plus End when $N = 0$ , and step 5 runs only when $N = 1$ . Then End gains the terms $T_4 \cdot \text{BRN} \cdot \overline{N} + T_5 \cdot \text{BRN}$ , and $\text{PC}_{in}$ gains $T_5 \cdot \text{BRN}$ .

Algorithms and pseudocode

Text

DERIVE-EQUATIONS(sequences)            // sequences[I][i] = set of signals in step i of I
  for each signal X
      terms <- empty
      for each fetch step i with X in fetch[i]
          add "T_i" to terms
      for each instruction I, step i with X in sequences[I][i]
          add "T_i AND I" to terms       // add the condition factor if the step is conditional
      X <- OR of terms

Text

CONTROL-CYCLE()                        // hardware behaviour every clock edge
  if End then counter <- 0
  else if Run then counter <- counter + 1
  T_lines <- decode step label T_(counter + 1) from counter;  I_lines <- decode(IR.opcode)
  every control signal <- its equation(T_lines, I_lines, flags, MFC, IRQ)

Mathematical explanation

Counter and decoder size. Encode step label $i$ by stored counter value $i-1$ ; labels $1,\ldots,n$ are not literal stored values. Reset to 0 and decode $T_{\text{counter}+1}$ . If the longest control sequence has $n$ steps, the counter needs $\lceil \lg n \rceil$ bits and the step decoder is $\lceil \lg n \rceil$ -to- $2^{\lceil \lg n \rceil}$ , of which $n$ outputs are used. An opcode of $p$ bits gives a $p$ -to- $2^p$ instruction decoder.

FSM flip-flops. A control FSM with $S$ states needs at least $\lceil \lg S \rceil$ flip-flops; one-hot uses $S$ .

Gate count of one signal. A signal with $t$ product terms needs $t$ AND gates (fewer where a term is a lone $T_i$ ) and one $t$ -input OR gate.

Worked examples

Example 1: sizing

A processor's longest control sequence has 12 steps and the opcode is 6 bits. Counter: $\lceil \lg 12 \rceil = 4$ bits; step decoder 4-to-16 with 12 outputs used; instruction decoder 6-to-64.

Example 2: reading an equation

From the table above, $Z_{in}$ is active in four (step, instruction) situations: step 1 of every instruction, step 5 of ADDR, step 6 of ADDM and step 4 of BR. During ADDM, $Z_{in}$ is therefore active in steps 1 and 6 only. $Z_{in}$ needs three 2-input AND gates (the $T_1$ term needs none) and one 4-input OR gate.

Example 3: FSM states

A control unit is designed as an FSM with 3 fetch states shared by all instructions, and execute states of 3, 4, 2 and 2 steps for four instructions: $3 + 3 + 4 + 2 + 2 = 14$ states. Binary encoding: $\lceil \lg 14 \rceil = 4$ flip-flops; one-hot: 14. If the execute states of different instructions are merged by step number (a step counter plus the opcode in IR), the counter needs only $\lceil \lg 7 \rceil = 3$ bits for at most $3 + 4 = 7$ steps.

Example 4: conditional branch timing

BRN takes 4 steps when not taken (End in step 4) and 5 when taken. With 30% of BRN taken, the average is $0.7 \times 4 + 0.3 \times 5 = 4.3$ steps.

Important properties and observations

One equation per control signal, a sum of (step AND instruction AND condition) terms.
Fetch steps contribute bare $T_i$ terms, since every instruction shares them.
End resets the counter; Run freezes it during memory waits.
Condition codes enter as extra AND factors, so a conditional instruction can end early.
Hardwired control is fast but rigid: a new instruction means new logic.
The control unit is an FSM; a step counter is a compact state encoding.
Common misconceptions.
- "Hardwired control cannot handle variable-length sequences." End can occur in any step.
- "Microprogrammed control is faster because it is programmable." It is slower; a control memory read is added to each step.
- "The counter must count to the number of instructions." It counts steps of the longest sequence.

GATE examination perspective

SIGNAL EQUATION. Scan every column of the control-sequence table for the signal; OR the (step AND instruction) terms.
COUNTER SIZE. $\lceil \lg(\text{longest sequence}) \rceil$ bits with zero-based stored step encoding.
FLIP-FLOPS. $\lceil \lg S \rceil$ binary, $S$ one-hot.
CONDITIONAL INSTRUCTIONS. Add the flag as an AND factor; count steps for both outcomes.
COMPARISON. Hardwired: fast, RISC, hard to change. Microprogrammed: flexible, CISC, slower.
AVERAGE STEPS. Weight each path by its probability.

Summary

CPU Datapath and Instruction Cycle: prerequisite. The control sequences being implemented.
Sequential Circuit Design and Finite State Machines: prerequisite. Counters and FSM state encoding.
Microprogrammed Control Unit: related. The alternative that stores the control sequences in memory.

Hardwired Control Unit

Introduction

Prerequisites

Core concepts

Building blocks

Control signal equations

As a finite state machine

Hardwired against microprogrammed

How it works

Worked derivation

Algorithms and pseudocode

Mathematical explanation

Worked examples

Example 1: sizing

Example 2: reading an equation

Example 3: FSM states

Example 4: conditional branch timing

Important properties and observations

GATE examination perspective

Summary

Sources

Next steps

Introduction

Prerequisites

Core concepts

Building blocks

Control signal equations

As a finite state machine

Hardwired against microprogrammed

How it works

Worked derivation

Algorithms and pseudocode

Mathematical explanation

Worked examples

Example 1: sizing

Example 2: reading an equation

Example 3: FSM states

Example 4: conditional branch timing

Important properties and observations

GATE examination perspective

Summary

Related topics

Sources

Next steps