I/O Interface and Interrupts: short notes (Computer Organization & Architecture)

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Introduction

An I/O interface (device controller, I/O module) connects a peripheral to the system bus. It contains a few registers that the processor reads and writes: a data register, a status register (ready, busy, error) and a control register (commands, interrupt enable). The processor can move data through these registers in three ways: programmed I/O, where it polls the status register in a loop; interrupt-driven I/O, where the device signals the processor when it is ready; and direct memory access (DMA), where the interface moves blocks to and from memory itself.

GATE asks you to compute the fraction of processor time that polling or interrupt servicing costs, to explain what the processor does when an interrupt arrives, to resolve priority among simultaneous requests (daisy chain, priority levels, masking), and to trace nested interrupts on a timeline. DMA is the subject of Direct Memory Access.

Prerequisites

CPU Datapath and Instruction Cycle: the instruction cycle and its interrupt check at the end of each instruction.

Core concepts

Addressing I/O registers

Scheme	How device registers are reached	Consequence
Memory-mapped I/O	They occupy addresses in the memory address space; ordinary LOAD and STORE access them	No special instructions; part of the address space is used up
Isolated (I/O-mapped) I/O	A separate I/O address space with IN and OUT instructions	Full memory space kept; extra instructions and a control line to tell the spaces apart

The three modes of transfer

Mode	Who moves each word	Processor cost	Best for
Programmed I/O	Processor, after polling status	Busy-waits for the device	Simple or very fast-responding devices
Interrupt-driven I/O	Processor, inside an interrupt service routine (ISR)	Only when the device is ready	Slow devices with irregular timing
DMA	The DMA controller	Set-up and one interrupt per block	Block devices such as disks and network interfaces

Interrupts

An interrupt request (IRQ) is a signal from a device asking for service. The processor recognises it only at the end of the current instruction, and only if interrupts are enabled (an interrupt-enable bit in the processor status register, plus per-device enable bits in each interface).

What the processor does on an interrupt:

Finish the current instruction.
Acknowledge the request (INTA) and identify the source.
Save the PC and the processor status (often on the stack).
Disable further interrupts (or raise the priority level).
Load the PC with the ISR address (from a vector table for vectored interrupts).
The ISR saves any registers it uses, services the device (which clears its request), restores registers and executes return from interrupt, which restores the PC and status (and so re-enables interrupts).

Interrupt latency is the time from the request to the first instruction of the ISR; it includes finishing the current instruction and saving the state.

Flowchart of interrupt handling: the device raises IRQ, the processor finishes the current instruction and checks whether the request is accepted, acknowledges it, saves PC and status, loads the vector, runs the ISR and returns from the interrupt. — Figure 1. Interrupt handling: the request is checked at the end of an instruction; if accepted, the processor acknowledges it, saves the PC and status, jumps through the vector to the ISR, and the return-from-interrupt instruction restores the saved state.

Several devices

Polling (software identification): one IRQ line shared by all; the ISR reads each device's status register in a fixed order. The order is the priority. Simple but slow.
Vectored interrupts: the device supplies a code (vector) identifying its ISR during the acknowledge cycle.
Daisy chain: the INTA line passes serially from device to device. A device that has not requested passes INTA on; one that has requested keeps INTA and places its vector on the bus. Priority is fixed by position: closest to the processor wins.
Priority levels: separate request lines with a priority encoder, or several daisy chains at different levels. The processor runs at a current priority; it accepts only requests above it.
Masking: an interface or a mask register can disable individual requests.
Nesting: if an ISR runs with interrupts enabled at its own priority, a higher-priority request can interrupt it; lower and equal ones wait.

Daisy-chained interrupt acknowledge through four devices — Figure 2. Daisy chain: four devices share one interrupt-request line; the acknowledge INTA enters device 1 and passes from device to device until it reaches the first requesting device, which keeps it and answers, so device 1 has the highest priority and device 4 the lowest.

Exceptions

Besides device interrupts, the same mechanism handles exceptions raised by the processor itself: errors such as an illegal opcode or a page fault, debugging traps, and software interrupts (trap instructions) used to make system calls into the operating system; see Operating System Structure and System Calls.

How it works

Polling against interrupts

With polling, the processor pays for every status check, whether or not the device has data. With interrupts, it pays only when the device is ready, but each service costs more (state save, ISR entry and exit). If the device is ready on almost every poll, the two cost about the same; for an idle or slow device, interrupts are much cheaper.

Algorithms and pseudocode

The programmed-input routine below uses indices 1..n. For ISR-INPUT, configure the shared buffer, count and n before enabling interrupts: n >= 1, buffer indices 0..n-1, count initially 0.

Text

PROGRAMMED-INPUT(device, buffer, n)
  for i <- 1 to n
      while device.status.ready = 0          // busy-wait
          do nothing
      buffer[i] <- device.data               // reading clears ready

ISR-INPUT()                                  // interrupt-driven
  save registers
  buffer[count] <- device.data;  count <- count + 1
  if count = n then device.control.interruptEnable <- 0
  restore registers
  return from interrupt

Mathematical explanation

Polling overhead. If the processor polls a device $r$ times per second and each poll costs $c$ cycles on a clock of $f$ Hz:

\text{fraction of processor time} = \frac{r \cdot c}{f}.

To avoid losing data, $r$ must be at least the rate at which the device produces units of transfer.

Interrupt overhead. If the device interrupts $r$ times per second and each interrupt costs $c_{\text{int}}$ cycles (entry, ISR body and return):

\text{fraction} = \frac{r \cdot c_{\text{int}}}{f}.

Maximum rate of programmed I/O. If the transfer loop takes $c$ cycles per unit, the processor can move at most $f / c$ units per second.

Worked examples

Example 1: polling overhead

A 2 GHz processor spends 500 cycles per poll.

A keyboard polled 50 times a second: $50 \times 500 / (2 \times 10^9) = 0.00125\%$ .
A disk delivering 8 MB/s in 16-byte units must be polled $8 \times 10^6 / 16 = 5 \times 10^5$ times a second: $5 \times 10^5 \times 500 / (2 \times 10^9) = 12.5\%$ .

Example 2: switching the disk to interrupts

The same disk raises one interrupt per 16-byte unit, at 1000 cycles per interrupt. While transferring, the cost is $5 \times 10^5 \times 1000 / (2 \times 10^9) = 25\%$ , worse than polling, because the disk is always ready. If the disk is transferring only 10% of the time, the interrupt cost averages $2.5\%$ , while polling fast enough not to miss data still costs 12.5% all the time. This is why block devices use DMA, which interrupts once per block.

Example 3: daisy chain

Four devices D1 (nearest the processor) to D4 share a daisy chain. D2 and D4 request at the same time. INTA passes through D1 (no request), stops at D2, which is serviced; D4's request stays pending and is serviced after D2's ISR returns (if no higher request appears). Moving D4 to the first position would make it the highest priority.

Example 4: nested interrupts

Three devices with priority D1 $>$ D2 $>$ D3 request at $t = 0$ (D3, ISR 30 $\mu$ s), $t = 10$ (D2, ISR 20 $\mu$ s) and $t = 15$ (D1, ISR 10 $\mu$ s). Overheads are ignored.

Policy	D3 finishes	D2 finishes	D1 finishes	D1 waits
Nesting allowed (higher priority preempts)	60	40	25	0
No nesting (ISRs run to completion, then highest pending first)	30	60	40	15

With nesting: D3 runs 0 to 10, D2 runs 10 to 15, D1 runs 15 to 25, D2 resumes 25 to 40, D3 resumes 40 to 60. Without nesting, D3 runs to 30, then D1 (30 to 40) beats the earlier D2 (40 to 60).

Example 5: programmed I/O speed limit

A polling loop takes 5 instructions per byte at 2 cycles each on a 100 MHz processor: at most $10^8 / 10 = 10^7$ bytes per second (10 MB/s), with the processor doing nothing else.

Important properties and observations

Interrupts are recognised only between instructions, so latency includes the rest of the current instruction.
The processor saves at least the PC and status; the ISR saves the registers it uses.
Interrupts are disabled on entry so that the same request does not re-interrupt before the device clears it.
Daisy-chain priority is fixed by position; the nearest device always wins, so a far device can starve.
Nesting lowers the latency of urgent devices at the cost of a deeper saved-state stack.
Polling wastes time on idle devices; interrupts waste time on always-ready fast devices.
Common misconceptions.
- "An interrupt stops the instruction in progress." Ordinary device interrupts wait for it to finish; only some exceptions (such as page faults) abort it.
- "Interrupt-driven I/O is always cheaper than polling." Not for a device that is always ready (Example 2).
- "In a daisy chain the device that requests first wins." Position, not timing, decides among pending requests.

GATE examination perspective

POLLING FRACTION. Polls per second times cycles per poll over the clock rate.
INTERRUPT FRACTION. Interrupts per second times cycles per interrupt over the clock rate; scale by the busy fraction.
SEQUENCE. Finish instruction, acknowledge, save PC and status, disable, vector, ISR, return.
PRIORITY. Daisy chain: nearest wins; priority levels: higher preempts if nesting is allowed.
NESTED TIMELINE. Draw the time axis; a preempted ISR resumes where it stopped.
MAPPING. Memory-mapped uses LOAD and STORE; isolated uses IN and OUT.

Summary

Sources

C. Hamacher, Z. Vranesic, S. Zaky, Computer Organization, 5th ed., McGraw-Hill, 2002, Chapter 4, Sections 4.1 (Accessing I/O Devices) and 4.2 (Interrupts, including 4.2.1 Interrupt Hardware, 4.2.2 Enabling and Disabling Interrupts, 4.2.3 Handling Multiple Devices, 4.2.4 Controlling Device Requests and 4.2.5 Exceptions).
D. A. Patterson, J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 5th ed. (MIPS edition), Morgan Kaufmann, 2013: Section 4.9 (Exceptions); Appendix A, Section A.7 (Exceptions and Interrupts).
W. Stallings, Computer Organization and Architecture, 10th ed., Pearson: Sections 7.2 (I/O Modules), 7.3 (Programmed I/O) and 7.4 (Interrupt-Driven I/O).