Computer Organization & Architecture · topic
Pipeline clock from stage and latch delays, total time, speedup, efficiency, throughput and CPI; data hazards with space-time diagrams, stalls and forwarding; control hazards with branch penalties, prediction and delay slots; structural hazards and combined CPI.
Pipelining overlaps the execution of several instructions, the way an assembly line overlaps the building of several cars. The work of one instruction is cut into k stages (for example fetch, decode, execute, memory access, write back).
A hazard is a situation in which the next instruction in a pipeline cannot execute in its planned clock cycle without giving a wrong result. The pipeline must then either wait (a stall, also called a bubble) or use extra hardware that removes the conflict.
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